s32r45 u-boot GPIO configuration

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s32r45 u-boot GPIO configuration

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eddy_bts
Contributor III

s32r45's gmac default is 'rgmii' so that gmac0 tx clock is currently output.

We should change tx clock as input in order to use 'mii'

Accordingly, s32r45-pinctrl.h file has been changed as follow

eddy_bts_0-1655722805758.png

In T32, modification above is not applied to register

eddy_bts_1-1655722928371.png

Any advice?

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alejandrolozan1
NXP Employee
NXP Employee

Hi Eddy,

I just tried this out on BSP32 and it seems to work:

alejandrolozan1_0-1655920535195.png

 

The change you made is exactly the one I did on Uboot:

diff --git a/include/dt-bindings/pinctrl/s32r45-pinctrl.h b/include/dt-bindings/pinctrl/s32r45-pinctrl.h
index 3a80e52925..5c60a6f030 100644
--- a/include/dt-bindings/pinctrl/s32r45-pinctrl.h
+++ b/include/dt-bindings/pinctrl/s32r45-pinctrl.h
@@ -251,7 +251,7 @@
/* PE02 */
#define PE02_MSCR_S32R45 (66)
#define PE02_GMAC0_TX_CLK_CFG (SIUL2_MSCR_S32_G1_MUX_ID_1 | \
- ENET_CLK_PIN_CFG)
+ ENET_IN_PIN_CFG)
#define PE02_GMAC0_TX_CLK_IN (SIUL2_MSCR_S32_G1_MUX_ID_2)

/* PE03 */

 

  • I just rebuild uboot:

make s32r45evb_defconfig

make CROSS_COMPILE=/<To toolchain path>/gcc-arm-10.2-2020.11-x86_64-aarch64-none-linux-gnu/bin/aarch64-none-linux-gnu-

 

  • Rebuild ATF:

make CROSS_COMPILE=/<To toolchain path>/gcc-arm-10.2-2020.11-x86_64-aarch64-none-linux-gnu/bin/aarch64-none-linux-gnu- ARCH=aarch64 PLAT=s32r45evb BL33=/<To Uboot Path>/u-boot/u-boot-s32.bin

  • And flashed the fip.s32

sudo dd if=fip.s32 of=/dev/mmcblk0 skip=512 seek=512 iflag=skip_bytes oflag=seek_bytes conv=fsync,notrunc

If you are following these steps it is likely that the image is not being updated. 

 

Saludos,

Alejandro

 

 

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eddy_bts
Contributor III

Thanks. It was my miss. I works well

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alejandrolozan1
NXP Employee
NXP Employee

Hi Eddy,

I just tried this out on BSP32 and it seems to work:

alejandrolozan1_0-1655920535195.png

 

The change you made is exactly the one I did on Uboot:

diff --git a/include/dt-bindings/pinctrl/s32r45-pinctrl.h b/include/dt-bindings/pinctrl/s32r45-pinctrl.h
index 3a80e52925..5c60a6f030 100644
--- a/include/dt-bindings/pinctrl/s32r45-pinctrl.h
+++ b/include/dt-bindings/pinctrl/s32r45-pinctrl.h
@@ -251,7 +251,7 @@
/* PE02 */
#define PE02_MSCR_S32R45 (66)
#define PE02_GMAC0_TX_CLK_CFG (SIUL2_MSCR_S32_G1_MUX_ID_1 | \
- ENET_CLK_PIN_CFG)
+ ENET_IN_PIN_CFG)
#define PE02_GMAC0_TX_CLK_IN (SIUL2_MSCR_S32_G1_MUX_ID_2)

/* PE03 */

 

  • I just rebuild uboot:

make s32r45evb_defconfig

make CROSS_COMPILE=/<To toolchain path>/gcc-arm-10.2-2020.11-x86_64-aarch64-none-linux-gnu/bin/aarch64-none-linux-gnu-

 

  • Rebuild ATF:

make CROSS_COMPILE=/<To toolchain path>/gcc-arm-10.2-2020.11-x86_64-aarch64-none-linux-gnu/bin/aarch64-none-linux-gnu- ARCH=aarch64 PLAT=s32r45evb BL33=/<To Uboot Path>/u-boot/u-boot-s32.bin

  • And flashed the fip.s32

sudo dd if=fip.s32 of=/dev/mmcblk0 skip=512 seek=512 iflag=skip_bytes oflag=seek_bytes conv=fsync,notrunc

If you are following these steps it is likely that the image is not being updated. 

 

Saludos,

Alejandro

 

 

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petervlna
NXP TechSupport
NXP TechSupport

Hello,

I have asked our R45 application engineer for help.

Once I have any answer I will feedback you.

Best regards,

Peter

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