UM10851: SJA1105EL: 5.1.1.2 Configuration status information: when does it ever change

GlennKessler · ‎07-12-2023

Hello,

I've got an SJA1105, device id 9E00030Eh, which I am trying to configure via SPI.
As for documentation, I refer to UM10851 and AH1601.

When do the flags in the Initial device configuration flag register change ?
So far the only thing in this register that has been changing is the counter NSLOT. All other bits have been 0 at any given time of reading.

What did I do?
Via SPI I have been able to read several DWORDS from base addr 0x00000.
Also adding the offset of specific registers worked as well.
(I read several double-words at a time, and, using the debugger I can see their values)

Reading from 0x00000 + 0 returns 0E03009Eh (is that byte order expected?)
Reading from 0x00000 + 1, returns the Initial device configuration flag register (see Table 15. in UM10851)

Directly after a power-cycle, before any SPI write operations, I believe the (binary) value of the initial device configuration flag register should read as follows:

0111 0000.0000 0000.0000 0000.0000 xxxx

I expect 0, since CONFIGS tells whether a configuration has been loaded.
I expect 1, since CRCCHKL tells whether the crc of the last local block was correct.
I expect 1, since IDS tells whether the device id has been written to 0x20000+0.
I expect 1, since CRCCHKG tells whether the crc of the last global block was correct.

Instead the register reads this:

0000 0000.0000 0000.0000 0000.0000 xxxx

Additionally, writing the device id to 0x20000 + 0
(I tried 9E00030Eh as well as 0E03009Eh),
I believe the flag IDS in the initial device configuration flag register should change from 1 to 0.
Only, the flag never was 1 in the first place.

I tried this using the generic loader format as described in 4.1.1
AH1601 mentions that only the crc is checked, not the logic of the configuration itself.
I therefore assume, writing an all '0' configuration, with checksums reflecting these values as well as the respective block id and block length should work just fine.

Without success I've tried downloading example configuration from SJA1105-tool.

Q1) Is the initial device configuration register supposed to be all zero after power-on/reset?
(except for NSLOT, bits 3:0)

Q2) Is the flag IDS supposed to change directly after the device id has been written to 0x20000+0?
(or does IDS only change after a complete load of the static configuration?)

Q3) Is the byte order I am seeing (Reading 0x00000+0 returns 0E03009Eh) correct?

Q4) in addition to Q1) assuming the SJA1105 calculates crc accross it's configuration in address region 0x20000, is this region initialized all '0' ?

Q5) When writing a device configuration, but before finishing, is reading the device configuration register allowed?
e.g. Let's say I've written the device id, the block id, block length and crc plus the data of this block and crc, and NOW I want to read the device configuration register.
Would that interrupt the loading of a device configuration?

GlennKessler · ‎06-13-2024

Hello again,

I've been able to successfully download a configuration onto a SJA1105TEL.
This was done in one cosecutive SPI transaction (during which chip select held it's state).
The configuration written is 'sja1105T_simple' taken from:

NXP Software Content Register
Release Name: Switch Configuration tool for SJA1105x
Version: 1.1

I'm afraid I have to ask you regarding the segmented download.
AH1601 suggests that multiple (segmented) SPI transactions are supported.

Section 4.3 Loading a Configuration to the Device:
...
This configuration can then be written into the switch by one (or multiple) SPI write transactions.
... A typical loading process is
shown in Fig 11. Here, the configuration data is split into two SPI transactions. The cut
does not need to be aligned with the generic payload format and can happen at any 32-
bit boundary. The process starts with a write transaction to address 0x20000. The first
double-word must be the device id (which must match with the device id of the silicon
revision4). After this, the device is unlocked for configuration and the configuration stream
is expected. Subsequent write transaction must be issued to an address different then
0x20000. For instance the address can be incremented as indicated by the figure.

...

Q6) how is Offset calculated?
Q7) may chips select change state in between Chunk1 and Chunk2

Attached is the pure configuration data as double-words, without any code, as well as a trace of the successful transaction (view with Logic 2.4.14).

(Edit comment: change iteratiors on questions to Q6 and Q7 in order to prevent confusion)

GlennKessler · ‎06-14-2024

Q6) how is Offset calculated?
- I tried a simple increment of 1 to the address 0x20000 and that worked

Q7) may chips select change state in between Chunk1 and Chunk2
- since the Initial device configuration flag register reads back 0x80000000, yes, the state of chip select (enable) may change

also see attached trace

mcagriaksoy · ‎02-15-2024

Hello all,

How did you read the address 0x000000 via SPI. I have created a frame like:

write flag = 0, read counter = X, address = 0x00.. , rest is zero. As described in this figure:

I am using SJA1105T chip. I guess its device id is: 0x9E00030E

But I receive : 0x8E00030E

Do you know anything related this received message, did I miss something?

Pseudocode:

frame.addr = 0x00, frame 0x2000000 or 0x1000000 or 0x0000000 in case of differenc "read counter"
spi_transmit(frame)
spi_receive(data)
"data" will be 0x8E00030E

GlennKessler · ‎09-19-2023

Hello Lukas again,

the device ID 9E00030Eh is given in both, UM10944 and UM10851.

I find this confusing. So, which is which?

GlennKessler · ‎07-13-2023

Hello Lukas, thank you. This helps me.

with regards

Glenn

lukaszadrapa · ‎07-13-2023

Hi,

First of all, device ID 0x9E00030E belongs to SJA1105TEL, so this is the correct user manual:

https://www.nxp.com/webapp/Download?colCode=UM10944

Not the UM10851.

Q1) Is the initial device configuration register supposed to be all zero after power-on/reset?
(except for NSLOT, bits 3:0)

- No, CRCCHKL, IDS and CRCCHKG are not supposed to be set after power on. There’s a note below the table (Table 26 in UM10944) which says that these flags are cleared after power on.

Q2) Is the flag IDS supposed to change directly after the device id has been written to 0x20000+0?
(or does IDS only change after a complete load of the static configuration?)

- The flags are supposed to be checked once whole configuration image is loaded. Not right after writing of ID.

Q3) Is the byte order I am seeing (Reading 0x00000+0 returns 0E03009Eh) correct?

- Yes, it’s just little endian format. It depends on microcontroller you use.

Q4) in addition to Q1) assuming the SJA1105 calculates crc accross it's configuration in address region 0x20000, is this region initialized all '0' ?

- The configuration image is supposed to be loaded as a continuous stream, so it doesn’t matter if the region is initialized.

Q5) When writing a device configuration, but before finishing, is reading the device configuration register allowed?
e.g. Let's say I've written the device id, the block id, block length and crc plus the data of this block and crc, and NOW I want to read the device configuration register.
Would that interrupt the loading of a device configuration?

- I’m not really sure about this but I wouldn’t do that. As mentioned above, the best option is to load the image as continuous stream.

Regards,

Lukas