TJA1101 sleep\wake up issue

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TJA1101 sleep\wake up issue

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PhanDoan
Contributor II

Hi guys,

I'm working with TJA1101 connected with Fs6500 following connection.png.

  • PHYAD1 is pulled to Vaux (3.3v) of Fs6500. 
  • PHYAD2 is pulled to GND.
  • The PORST pin of MCU and RST_N pin of TJA1101 is connected to The RSTB pin of Fs6500.
  • VDD(io) of TJA1101 is connected to Vaux of Fs 6500.

I'm having an issue with the Phy wasn't able to wake up after I triggered to sleep and wake up the whole system with the Fs6500 and I also observed a strange behavior of pin strapping. 

Step to reproduce: 

1) Open the KEY_SW and request the SPI command to make Fs6500 go to  LPOFF - SLEEP mode (the MCU will be off after that). The TJA1101 went to sleep mode since Undervoltage was detected.  

2) Wake the whole system by closing the KEY_SW.

3) Wake the Phy by sending the standby mode command with PHYAD[4:0] = 0b00010 (following the pin strapping configuration) at MCU initialization. 

 Expected result:

The Phy should be able to wake up and be in normal mode.

 Actual result: 

The Phy wasn't able to wake up.

4) After step 3), I read all registers of TJA1101A using PHYAD[4:0] =  0b00000  and observed that the PHYAD[4:0] was 0b00000 ( step4.png) 

step4.png

5) I woke the Phy by sending the standby mode command with PHYADD[4:0] = 0b00000. The Phy was able to wake up, but it seems like somehow the strap-pin was performed and the PHYADD[4:0] had the value 0b00010 after that. ( step5.png) 

PhanDoan_0-1637834166346.png

Could anyone help me to explain this strange behavior?

Thank you.

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Bulat
NXP Employee
NXP Employee

It looks like pin strapping does not happen in your case at step 3. Note, if you apply VBAT only (no 3.3V supplies), the device will tranfer to sleep mode without pin strapping event. As soon as 3.3V applied, it is not possible to wake up the device using 0b00010 address because it (strapping configuration) has not been sampled yet. As soon as pin strapping occurs, address 0b00010 becomes functional.

 

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PhanDoan
Contributor II

Thank you for your answer,

Yes, you're right, The pin strapping should not happen at step 3), but the PHYAD[4:0] was 0b00010 before I triggered to sleep the system with the Fs6500.

Because of that, I expected that I could be able to wake the Phy with the PHYAD[4:0] = 0b00010. Sadly, It didn't happen. 

The picture below is the register value before the system went to sleepmode. (before step 1) 

before step1.png

So I wonder that why the value of  PHYAD[4:0] was 0b00000 After I woke the system and why I could not wake the Phy with the PHYAD[4:0] = 0b00010 ... 

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Bulat
NXP Employee
NXP Employee

Is it possible that the MCU drives reset (PORST) when the system goes to sleep?

 

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PhanDoan
Contributor II

Yes, in theory, when the low-power mode was requested to the SBC, the SBC released the RSTB pin  (went to low level) before switching off the Vaux and they will be at the high level again after ECU woke up. Is there a connection that could lead to the change of the PHYAD? 

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Bulat
NXP Employee
NXP Employee

Yes, RST signal resets configuration of the TJA, so previous strapping setup is lost.

Note, PHY address 0x0 is not  "new" or reset address, it is always there. If you set the address to e.g. 0x2 during pin strapping, address 0x0 is still applicable. If you have a single PHY on the SMI, you can use address 0x0 permanently.

 

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PhanDoan
Contributor II
Thank you for your suggestion to use the address 0 to communicate with the TJA. Since we currently have a single PHY, we applied it as a workaround solution. 
 
My theory is that when the low-power mode was requested to the SBC, it released the RSTB pin before switching off the Vaux. That led to the Phy entering the reset mode (the ETH_RST is connected to the RSTB pin of Fs6500) first and then switching to standby mode because the Phy detected the Undervoltage on VDD(IO) pin.
 
When switching from reset to standby mode, pin strapping was performed. Because Vaux3p3 was low at that time, it made the PHYAD have the value 0 (Pin23 and Pin24 were at low-level). 
 
Finally, the Phy switches to Sleep mode after Tto(uvd).
Pin_strapping_behavior.png
 
 
Hence, I still don't know why the PHYADD value switch back to PHYAD[4:0] = 0b00010 after I woke the system up (step 5). I expected PHYAD[4:0]  should be 0b00000 since pin strapping is only performed when the PHY enters Standby mode after power-on and it will only be repeated after a hardware reset via the RST_N pin. I believe that the TJA couldn't go to the reset mode even if the RST_N pin had a low-level pulse during system wake-up because it was in sleep mode.
TJA_reset.png

 
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Bulat
NXP Employee
NXP Employee

Possible scenario can be as following:

1. RSTB signal low resets the PHY but pin strapping does not happen because 3.3V immediately disappears (pin strapping can not happen without 3.3V supply). As a result the PHY goes to sleep mode after Tto(uvd) without configuration, i.e. reset sequence does not complete.

2. As soon as 3.3V applies and you wake up the PHY (using address 0x0), it runs pin strapping due to previous reset event, so completes reset sequence.

 

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