PN7150 TVDD configuration

[dc1]

Hello,

we have a board with the PN7150 where the power supply is give as in the AN11756 - 6.4.1 Config 1: VBAT used to generate TVDD. The VBAT and the VBAT1,VBAT2 are connected to a 3.3V LDO.

The problem is when the chip NFC go in Polling phase, we have a disturb on the 3.3V LDO that return on the 5V that is generated by a DC/DC. This disturb generate problems with the Radar on the device. 

My idea is that the NFC chip generate this problel when switch the TVDD from 2.5V in standby mode to the 3.3V, that is the default value in the register PMU_CFG (see User Manual  pag.88) . The problem is that the VBAT is not ≥ (3.3 + 1Ω ∗ Itx). We need so to set the TVDD to 3V. 

From the kernel driver https://github.com/NXPNFCLinux/nxp-pn5xx/blob/master/pn5xx_i2c.c we can set these value in the DTS:

struct regulator *pvdd_reg;
struct regulator *vbat_reg;
struct regulator *pmuvcc_reg;
struct regulator *sevdd_reg;

on what register they acts? Can we configure the PMU_CFG setting these values? There is an example for do that?

Thanks

[andreastruppe]

破坏者

Hi

can you provide us your schematics and design files for review?

[dc1]

Hello, 

thanks for the information. Tried different solutions but the noise generated from the NFC chip affect the radar. This noise generated on the 3.3V return back on the 5V dc-dc and this arrive to the radar. The solution find was to power supply the radar with a different power supply. 

Why the nfc chip generate so many noise? there are filters to be applied on the vdd ?

[danielchen]

Hi dc:

PMU_CFG can be configured in libnfc-nxp.conf .

###############################################################################
# TVDD configurations settings
# Allow NFCC to configure External TVDD
# There are two possible configurations (0x01 or 0x02):
# CFG1: Vbat is used to generate the VDD(TX) through TXLDO
# CFG2: external 5V is used to generate the VDD(TX) through TXLDO
NXP_EXT_TVDD_CFG=0x02

# CFG1: 3.3V for both Reader and Card modes
NXP_EXT_TVDD_CFG_1={20, 02, 07, 01, A0, 0E, 03, 02, 09, 00}

# CFG2: VBAT2 to 5V and 4.7V for both Reader and Card modes
NXP_EXT_TVDD_CFG_2={20, 02, 07, 01, A0, 0E, 03, 06, 64, 00}

The last 3 bytes "02 09 00" or "06, 64,00" are the parameters.

Regards

Daniel