Lower limit of fall time included in I2C specifications (UM10204)

[tnasu]

Dear Sirs,

Upper and lower limit values are specified for the fall time of SDA and SCL signals in the UM10204. Please tell me the reason why the lower limit value is set. I've seen on another site that EMC is involved, is that correct?
If so, is there no need to meet the lower limit without considering the impact on EMC? The fall time of the board currently under development is too short, so it falls below the lower limit.

Best Regards,

[guoweisun]

Hi

Yes, you can comprehend that specified slew rate limiting to reduce electromagnetic interference from the fast transitions.

[tnasu]

Thank you for your reply.
There are some lines of our board where the fall time is faster than the minimum value.
However, the I2C timing specification of the connected device did not specify a minimum fall time. (maximum value only)
Also, the communication is not continuous, but only at intervals of a few seconds at most. I think that the effects of electromagnetic interference will be minimal, so in such a case, is there any problem even if the minimum fall time is not met?

[guoweisun]

Never try this but that should be no problem, you can try and let us know the result.