FS6500 Ignition Input Scenerio

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FS6500 Ignition Input Scenerio

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Aozpay
Contributor II

Hello,

I am using FS6500 series SBC with fail-safe configuration. (Select resistor connected to GND).

But something confuse my mind. According to main state and fail safe state machines(Below) if SBC goes to normal mode ONCE, SBC can not go to LPOFF mode with ignition input. Is this right?

 

Aozpay_0-1618477944134.png

Best Regards,

Alican OZPAY

 

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JozefKozon
NXP TechSupport
NXP TechSupport

Hi Alican,

The main state machine has three LPOFF modes with different conditions to enter and
exit each LPOFF mode.

LPOFF - sleep

Entering in low-power mode LPOFF - sleep is only available if the product is in normal
mode by sending a secured SPI command. In this mode, all the regulators are turned off
and the MCU connected to the VCORE regulator is unsupplied. Only VKAM is available if
VKAM is used.

Once the 35FS4500/35FS6500 is in LPOFF - sleep, the device monitors external
events to wake-up and leave the low-power mode. The wake-up events can occur and
depending of the device configuration from:
• CAN physical layer
• I/O inputs IO_0 is also na I/O input. To use it for wake-up from LPOFF-sleep you need to set WU_IO0_1:0 to 01.

JozefKozon_0-1618834827161.png

• Timer
LPOFF - auto WU

LPOFF - auto WU is entered when the device is in the INIT or normal mode and if the
VPRE voltage level is passing the VPRE_UV_L_4P3 threshold (typ 4.3 V). It can be also
entered by sending a secured SPI command if the product is in normal mode.

LPOFF - deep FS

LPOFF - deep FS is entered when the device is in deep fail-safe and if the key is off
(IO_0 is low). To exit this mode, a transition to high level on IO_0 is required. IO_0 is
usually connected to the key on key off signal.

When the deep fail-safe function is enabled, the fail-safe state machine monitors and
count the number of faults happening, in case of fault detection. As soon as either the fault error counter reaches its final value or the RESET pin remains asserted low for more than 8.0 s. 

 

If you want to enter one of the LPOFF modes without the software, only option I see, is to hold the reset RSTB pin low for at least 8 seconds and the IO_0 must be also low, then the SBC enters LPOFF-deep FS mode and by transition of IO_0 to high level the SBC exits the LPOFF-deep FS mode.

JozefKozon_1-1618835755240.png

 

With best Regards,

Jozef

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bharathn3402
Contributor II

Hi i have a question related to SBC fs6500
iam using SBC FS6500 i sent a command to go into LPOFF-Sleep and wait for wake up signal. in this case it is going to LPOFF-Sleep mode and waking up when iam giving wakeup signal. But randomly its not waking up when iam giving wakeup signal. what may be the reason?

 

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Aozpay
Contributor II

Thank you for your reply.

Can I only wake-up event with IO_0 without secured SPI command or Auto-WU? I want to build my opening and closing architecture according to ignition input status. But all regulator except for VKAM are closed on LPOFF mode. 

For example ignition input status is low, if my mcu do not send secured SPI command to SBC for the SBC goes to LPOFF mode, SBC will not go to LPOFF mode because my mcu do not send secured SPI command. Is this right? I want to my sbc to LPOFF mode indepented from software.

Best Regards,

Alican

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JozefKozon
NXP TechSupport
NXP TechSupport

Hi Alican,

The main state machine has three LPOFF modes with different conditions to enter and
exit each LPOFF mode.

LPOFF - sleep

Entering in low-power mode LPOFF - sleep is only available if the product is in normal
mode by sending a secured SPI command. In this mode, all the regulators are turned off
and the MCU connected to the VCORE regulator is unsupplied. Only VKAM is available if
VKAM is used.

Once the 35FS4500/35FS6500 is in LPOFF - sleep, the device monitors external
events to wake-up and leave the low-power mode. The wake-up events can occur and
depending of the device configuration from:
• CAN physical layer
• I/O inputs IO_0 is also na I/O input. To use it for wake-up from LPOFF-sleep you need to set WU_IO0_1:0 to 01.

JozefKozon_0-1618834827161.png

• Timer
LPOFF - auto WU

LPOFF - auto WU is entered when the device is in the INIT or normal mode and if the
VPRE voltage level is passing the VPRE_UV_L_4P3 threshold (typ 4.3 V). It can be also
entered by sending a secured SPI command if the product is in normal mode.

LPOFF - deep FS

LPOFF - deep FS is entered when the device is in deep fail-safe and if the key is off
(IO_0 is low). To exit this mode, a transition to high level on IO_0 is required. IO_0 is
usually connected to the key on key off signal.

When the deep fail-safe function is enabled, the fail-safe state machine monitors and
count the number of faults happening, in case of fault detection. As soon as either the fault error counter reaches its final value or the RESET pin remains asserted low for more than 8.0 s. 

 

If you want to enter one of the LPOFF modes without the software, only option I see, is to hold the reset RSTB pin low for at least 8 seconds and the IO_0 must be also low, then the SBC enters LPOFF-deep FS mode and by transition of IO_0 to high level the SBC exits the LPOFF-deep FS mode.

JozefKozon_1-1618835755240.png

 

With best Regards,

Jozef

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Aozpay
Contributor II

Thank you for the reply Mr Jozef.

The SBC is always on auto-wu mode If VPRE can pass VPRE_UV_L_4P3 threshold (typ 4.3 V) level when the SBC is in INIT_MAIN phase or normal mode? Does not auto-wu repeat itself per 1ms period always?

Best Regards,

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JozefKozon
NXP TechSupport
NXP TechSupport

Hi Mr. Alican,

according to the Main state machine in the datasheet if the VPRE voltage passes the VPRE_UV_L4P3=4.3V during the INIT or NORMAL mode the SBC enters the LPOFF-Auto WU mode.

JozefKozon_0-1619682144347.png

If the SBC will automatically tries to wake up itself from the LPOFF Auto WU mode, depends on how a bit 6 in MODE register is set. By default its 0, no action. It the bit 6 is set to 1, than the SBC will automatically tries to wake up from the LPOFF Auto WU mode after 1ms.

With Best Regards,

Jozef

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JozefKozon
NXP TechSupport
NXP TechSupport

Hello Alican,

The SBC can go in LPOFF SLEEP mode with the IO_0=1, but cannot go in LPOFF DEEP FS mode with the IO_0=1. So you are right if you meant the LPOFF DEEP FS mode, which is different from LPOFF SLEEP mode. While in LPOFF DEEP FS mode, the SBC can be woken up by bringing the IO_0 high. Therefore to enter the LPOFF DEEP FS mode, the IO_0 must be low.

JozefKozon_3-1618557859798.png

While in normal mode, the device can be set to low-power mode (LPOFF-SLEEP) using secured SPI command.

JozefKozon_2-1618557141590.png

With Best Regards,

Jozef

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yashjatushkaran
Contributor I

Hello @JozefKozon ,

I am doing something similar and using SPI secure command to Go from Normal mode to LPOFF mode inside FS6500

But i am not able to switch to LPOFF mode. Could you please tell me the prerequisites for achiving this.

Please find the commands i am sending below using SPI :

1. write INIT_INT        Tx 0x8900 Rx 0x0700

2. Read Mode Status Tx 0x2A00 Rx 0x8704

3. Write GoLPOFF      Tx 0xAA20 Rx 0x0704                 

4. Read Mode Status Tx 0x2A00  Rx 0x8704 --> Still inside Normal mode

Coudl you please guide me where i am going wrong?

Thanks in advance!

 

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JozefKozon
NXP TechSupport
NXP TechSupport

Hello Alican,

when you want to switch to LPOFF mode from Normal mode with secured SPI command, you should send the command consisting of two bytes in the pin MOSI.

JozefKozon_2-1628237161083.png

JozefKozon_3-1628237445262.png

JozefKozon_4-1628237472098.png

The bit9 through bit15 is an address. 1010101. 

You can enable or disable the VKAM. Lets say you will disable it. Bit7 will be 0, bit6 0, bit5 must be 1 to go to LPOFF mode, bit 4 will be 0.

The lowest four bits must be set according the section 7.2.6 in the datasheet. 

JozefKozon_5-1628237943820.png

Bit3=NOT(Bit5)=0

Bit2=NOT(Bit4)=1

Bit1=Bit7=0

Bit0=Bit6=0

The 2 bytes will be 1010101P 00100100

The P is the Parity bit, which should be calculated according the section 7.1.2 in the datasheet.

JozefKozon_6-1628238170708.png

Because the number of 1 in the bits 15–9, 7–0 sequence is even in this case, the Parity bit will be 1.

So the final 2 bytes will be 10101011 00100100=0xAB24.

Please note, that the NCS (Not chip select) must be low for the transmission. 

JozefKozon_7-1628238504424.png

 

With Best Regards,

Jozef

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