OSBDM - how I did it

[jarin]

Hi all.
Hope you don't mind a few words to illustrate how I got to my version of OSBDM.

Few months ago I built "original" OSBDM for HCS08, with two 74LVC1T45 buffers. That time I had virtually none experiences wit HCS08 family (alhough I worked for years with other MCU's). It worked perfectly for RD16 device and didn't work for QG8 device. Later I found out that only way how to get QG8 into debug mode is holding BKGD pin low while power-on reset (somebody from Freescale explained here on forum why it is so), adding button on my experimental board solved this. I found holding button everytime I need disconnect and reconnect my hardware (for circuit changes) annoying, that's why I looked for some way to do this automatically. That time update for OSBDM was issued (including support for RS devices, look on that long thread by Joerg). In that circuit is RESET circuitry omitted for HCS devices and for RS devices it is just to bring "high" voltage to target. That's why all HCS devices must start debug mode just with BKGD pin low while power-on reset (not only QG). This is handled with resistor and capacitor (transient on capacitor ensures low voltage for a short time on BKGD pin). I did further experiments with my OSBDM. LVC buffer for RESET pin was suspended (by removing appropriate 47R resistor) and I added RC (22kohms and 1uF) circuit + small schottky diode to BKGD pin, as necessary. I found out that this circuit is unreliably. Target very often didn't get into debug mode, thus OSBDM plus Hiwave wasn't able to connect it. Getting it into debug mode was always a long work.
I took my favourite simulation program and tried to simulate behaviour of this RC device on simulated power-on reset. It happens exactly what I expected. Considering that for Vdd=3V is Vil about 1V (according to datasheet 0.35*Vdd), voltage on BKGD pin will excess this in a few milliseconds, but get above Vih after about twice the time! Slowly changing "analog" voltage on digital input is in general ilegal and incorrect, that's why I tried to improve it a little bit. I added a transistor, resistor, decreased capacity, as you can see here, on this schematics:

http://www.jednocipy.kvalitne.cz/osbdm/osbdm-c1.gif

on power-on, capacitor is charging and transistor is opened because of current flowing into it's base. Volatage on BKGD pin is forced to low level. As capacitor is charging, voltage on it increases, currend through resistors decreases and volatage on R2 falls down. After a some time (given mostly by resistors and capacitor) volatage on R2 falls down below Vbe limit, transistor gets closed realtively fast (because of "knee" on VA characteristics of B-E junction, as well as other PN junctions) and BKGD pin is released as fast. R2 also ensures discharge of capacitor (discharging through this resistor and rest of whole debugged circuit) after power-down, to get OSBDM ready to start again. Voltage change (between low and high level) on it's collector is much faster compared to original circuit with only RC device. Here you can see oscillograms of simulation.

http://www.jednocipy.kvalitne.cz/osbdm/osbdm-c2.gif

I simulated two circuits at once, one with transistor and original one. Red curve means voltage on BKGD pin with transistor circuit, green one means voltage on the same pin with just RC device and diode. Blue arrow shows approximately start of transient (power-on). I think it's clearly to see difference.
Of course, I realised the circuit to verify my calculations. Targets (I tried both RD16 and QG8) supplied 3V from external LE30 regulator gets into debug mode much more reliable compared to original RD circuit. I'm quite satisfied with this circuit. I used old KC238 transistor from my junk-box. It's a small silicone transistor in TO92, older than I am. BC550, 2N3904 or any general purpose NPN transistor would do the job, probably.
And I also would be happy if somebody can try my small improvement to verify it's functionality again and report comments or suggestions.

I'm considering to built better device to hold BKGD pin low, with comparator and RC device. I added some MCP6546 comparators from Microchip to my last order and I'll try to use them for this purpose. I'll report about it.

I'm going to start to make PCB for this OSBDM, I'll place it and whole schematics here on forum when done.


I tried to describe it as clear as possible, in my native language it would be definitely better, but unfortunately it's not the case of English language.



Jarin

[bigmac]

Hello Jarin,

Another possibility might be to make use of a low voltage supervisory device, but connected to the BKGD pin rather than RESET.  Some of these devices provide a delayed release after the threshold voltage is reached.  For example, the Microchip MCP120 provides a typical delay of 350ms.  I assume other similar devices may have even longer built-in delay.

The MCP120 is available in a TO-92 package, and no other components should be necessary.

Regards,

Mac

[jarin]

Hello bigmac,
I also considered this possibility, but it those supervisory devices (powered from Vdd of target and controlling BKGD pin) play dead until supply voltage 1V, then it pulls reset down and wait those 350ms (and also checks supply voltage), as noted in datasheet. It may be source of problems with target running at low supply voltage for example 1.8V, as voltage rising on Vdd (and also on BKGD because of pull-up) on it's value 1V supervisor still does nothing, but this voltage is well above Vil limit for digital input and thus target may not enter debug mode and start to run program from FLASH instead. When supervisor pulls BKGD pin low, it's too late.
This behaviour is maybe OK for resetting MCU's, but definitely not good for entering HCS into debug mode.
In my device with transistor this happens too, but it starts to respond at definitely lower voltage. But after all, that's why I want to try analog comparator. It would be always powered by 5V from USB, so it will hold BKGD pin always until given time after Vdd of target rises some value.

[bigmac]

Hello Jarin,

Since you would only be using the supervisory device for its delay capability, and not its voltage threshold, you could apply power to the device from the input side of the voltage regulator, rather than the output side.  Of course, you would need to use a device with no internal pull-up resistor.  This should then be capable  of applying a low level to the BKGD pin prior to release of the internal LV reset of the MCU, following POR.

I assume you are regulating the USB 5V down to 3.3V to supply the MCU.  There would also be some advantage if the regulator type was not ultra LDO.

Regards,

Mac

Message Edited by bigmac on 2007-02-0510:44 PM

[jarin]

Hello Bigmac,

when you power-on any voltage regulator, you will see transient, because of nonzero internal resistance of it (it's not ideal volatage source), speed of response of its internal voltage feedback, load capacity and so on. This transient persist for some milliseconds to seconds, it depends of regulator (in fact, it persist indefinetely, because of exponential curve never meets zero, but after some definitely time we can say it's settled in some limits we can consider as stable).
We can expect this real voltage regulator feeds our HCS target. This also feeds supervisor, something like MCP120. Output of that supervisor is connected to BKGD pin to pull it down to zero while startup. Note that internal pull-up resistor is already inside HCS device (to ensure starting in run mode with no BDM tool connected). When you switch power to regulator, ti's output voltage starts to rise, with finitely derivation dV/dt. As this voltage rises (assuming it not exceeded that critical barrier 1V), almost the same voltage is on BKGD pin - because of that pull-up I mentioned and because under 1V supervisor is just dead piece of silicon and thus it does no pull-down. Just after rising above 1V it wakes up and because Vdd is still less than it's programmed value, it pulls BKGD pin low and waits until exceeds that value. Then it still holds BKGD pin low for 350ms. But there is problem. While the voltage was under 1V, BKGD pin was as high as supply voltage and no one can exactly say how the HCS will react on this. It may enter debug mode, as well as may run user code and OSBDM will not be successful to start debug session.
Putting supervisor before regulator will probably fix that, but this limits it to use with on-board voltage regulator. When using external supply, you are out of luck.
I'm still waiting for some comparators from microchip (my distributor got into some problems, but promised me it will be available this week, I hope), device with comparator will hold BKGD pin low while it reaches some limit and defined time after regardless if it's supplied from on-board regulator or external supply. It also allows to set how long will be the BKGD pin held low (by selecting passive components).

That thoughts about supervisor was my own analysis why I omit that from tests for suitable "hold-on-power-on device" (uuh!).


I'm sorry if I mangled some technical terms in English, I tried as much as possible not to do so.

[bigmac]

Hello Jarin,

If you need to trigger the start of the BKGD low delay from the Vdd side of the regulator, I agree you will need a much lower voltage threshold.  Looking at the POR rearm voltage for the various MCUs, for the more recent devices, the minimum threshold level seems to be 0.8 or 0.9 volt.  However, for the earlier GB/GT devices, the minimum threshold is normally 0.5 volt, but only 0.2 volt if re-arming from stop mode.

I note that the POR voltage specification has been omitted from QD data sheet (well I can't find it), and for the QG devices only a typical value is given, and not a minimum value.

The BKGD low delay start threshold would need to be less than 0.2 volt, to allow for the possible worst case situation.  Based on Joerg's recent observation, you may need to wait at least 3 seconds after removal of power, to achieve this level - I assume the period would be dependent on the size of the capacitor at the output of the regulator.  I wonder if the period might be reduced with an additional resistor, say 4k7, connected between regulator output and ground.

Regards,

Mac

[jarin]

Bigmac,
yes you're right, starting power-on delay for holding BKGD low is best when done from input side of regulator. It's easy when using regulator included on OSBDM board. But, I'm using (and I believe I'm not the only one) mostly external power supplies (not just for HCS) for debugging, so in this case it is somehow difficult. I'm impatiently expecting those comparators I mentioned above, I think they will universal solve the problem of power-on delay.
I already included 10kohm resistor into my OSBDM as a load for regulator, but it mostly behaves as load for discharging delay capacitor after powering-down (in fact, I that was the reason why I added it into circuit). As voltage falls down below 1V, maybe 0.5V, current consumption of MCU and all integrated devices rapidly decreases, that's why the last bites of charge on decoupling and bulk capacitors are discharging so slow (as Joerg mentioned above). In this scenario, resistor ensures discharging of "timing" capacitor through resistor R2 (as labeled on this schematics http://www.jednocipy.kvalitne.cz/osbdm/osbdm-c1.gif). I found out that time about 1-2 seconds after power-down is enough for powering-up again (of course, this strongly depends on overall capacity of capacitors included on power lines, in my case it's about 16 microfarads).


Unfortunately, now I found out I copied wrong version of schematics I created on weekend. The right one is on my computer at my home, so I will get it on this weekend. Next week I'll upload my schematics and report here, maybe with comparator device too.

Message Edited by jarin on 2007-02-0604:48 PM

[jarin]

Hello all,
I've been busy in last days and after some quite period I return to this thread. Here http://www.jednocipy.kvalitne.cz/osbdm/osbdm-schem1.gif you can see schematics of OSBDM I'm going to make. It looks terrible, I know, but it's just first version, when I got it working, I'll post updated (and more readable) one. Hope there are not any mistakes.
My OSBDM is just old OSBDM (with two drivers) and transistor circuit. RESET pin is not connected, so driver for RESET should be omitted as I did it in schematics.

Those days I'm doing also tests with comparator (as I wrote in posts above) - I removed transistor circuit and installed comparator circuit instead (connected just with wires, that kind of "quick and dirty" work). Also I'm waiting until friend of mine manufacture PCB for me - for the version with transistor. Yes, I'm doing two versions of OSBDM, hope the second one will be better.

If you feel unsure about my unclear description above (in fact I'm doing two things at once), please wait until I'll report news about my work. I'm busy those days, but I'm trying to work also on OSBDM.

Cheers, Jarin

[Alban]

Hi Jarin,

As you have probably seen on the 'sticky' posts, I am compilating a list of existing OSBDM08 variations so a newbie can chose and create exactly what he needs.

http://forums.freescale.com/freescale/board/message?board.id=OSBDM08&message.id=212

When you do your explanations in the next posts, please do include a list of keypoints which make you OSBDM original and depending on what it is based on, it will get a REVISION No and be put in the OSBDM08 table with links to your profile, sources and schematics.

That table is already the reference for OSBDM08.

Cheers,

Alban.

[jarin]

Hi again,
I just tried circuit with comparator MCP6546 with schematics like this http://www.jednocipy.kvalitne.cz/osbdm/osbdm-bsw-cpr.png

As you can see, it's easy. Just one comparator feed with stable 5V from USB. This voltage is also used to derive "reference" voltage. Term "reference" means here something keeping it's voltage in range of hundreds of milivolts, but this is absolutely enough for application like this.
When target voltage is applied (and capacitor is in discharged state), transient starts, capacitor starts to charge through resistor R4. As it charges, voltage on pin 3 rises from zero exponentially (resisitor R4 with R1 ensures discharging of capacitor after power is removed). Voltage on pin 3 is lower than on pin 2 on output of comparator is held low and also forcing BKGD pin to be low (note the output of this comparator is open-drain). When (after some time, given by timing constant) voltage on pin 3 exceeds voltage on pin 2, comparator flips to other state, it's output gets into high impedance and BKGD pin floats to high level because of pull-up resistor (there should be internal resistors in HCS devices).
Comparator plays dead until target supply voltage is lower than voltage on pin 2 (I measured in my device about 0,85V, calculated value is about 0.88V) and BKGD pin is held low during this period.
I tested it just with QG8, but I'm pretty sure it must work also with other HCS08.

Now I'm going to make new new PCB for this OSBDM with comaprator (my test circuit is built just on piece of universal board, it looks terrible and it's unusable as well).
So full schematics and PCB will be available later.


Alban: Yes, I will. I think this table is very good idea. Open source projects usually get smashed into many versions and this may help to prevent disorientation and confusion.

Message Edited by jarin on 2007-02-1406:35 PM

[bigmac]

Hello Jarin,

If you have not already tested with a target voltage of 5.5 volts, I might suggest you do so.

If my calculations are correct, the nominal delay is 22 milliseconds for a target voltage of 1.8 volts, but drops to only 5.7 milliseconds for 5.5 volts.  Depending on the rate at which the target voltage ramps up, this delay might not be sufficient for the POR process to complete.  Perhaps a significantly larger capacitor value would be safer.

Another possibility might be to use a lower value resistor in series with the 330k, and to clamp the voltage applied to the 330k using a zener, say 2.5 volts, or thereabouts.

Yet another possibility is to connect the 330k to USB +5V, and set a comparator threshold of say, 2.5 volts, to give a fixed delay of 22 milliseconds.  A second comparator section would then be used to discharge the capacitor whenever the target voltage was below a comparator threshold of 0.8 volts.  Apart from a dual comparator package, this would require one extra resistor from what you currently have.

What influenced your choice of MCP6546 device?  With what you are doing, I would expect that many more "common garden" devices would be equally as suitable, e.g. LM393 (actually a dual comparator).

Regards,

Mac

[joerg]

Hi
looking at all this schematics, i have reflected the case. I noticed, that all circuits do not consider the state of the level translator witch means, that the output can be shorted (even protected by a resistor) and this is also a situation i dislike.
My solution can be found in the attachment.
It uses a comparator to hold down the BDM data line during power up and forces the level translator to be input. A second comparator indicates the POR_OK state (BDM_V+ lower than 0.3V) so different circuits can be used. I would like to do a automatic POR circuit, but i think this is only possible with changing the firmware.

Saluti Joerg

Message Edited by joerg on 2007-02-1511:14 AM

BDM_POR.pdf

Message Edited by t.dowe on 2009-10-26 05:12 PM

[jarin]

Joerg: Good point. I thought about changing firmware of JB16 to hold BKGD pin low (external comparators would indicate to JB16 if it's the right time to release BKGD pin), but I do not feel I'm able to do this, but this would also remove problems with shorted output of driver.
Trying to do all things right gets to slightly more complicated solutions.

And I would also add transils to target Vdd and BKGD pins on OSBDM - to prevent destroying LVC drivers in a case of "accident" - I mean voltage spikes, even slight overvoltage or reversed power supply. 1,5kW transil (like 1,5KE6V8A) lasts more of "bad handling" compared to device in SOT23 (LVC driver).


Edit: when me manually change state of level translator to be input on BDM side - and output on JB16 side, doesn't JB16 mind it? JB16 output drivers can be also set to be output ant then it probably will configure LVC to be input on JB16 side. But when we don't care about JB16 setting and force LVC to be input on BDM side and output on JB16, in fact there are two outputs connected to one point. That is unacceptable.
I think in this case is necessary fimware change.

Message Edited by jarin on 2007-02-1510:53 AM

[joerg]

Hi jarin
i did not think on the JB16-LVC path, so i will have a look at the firmware, since this will be the cleanest way to resolve the problem. All the addon stuff seems to be some kind of non serious design practice using a lot of components, but not really resolving the problem.

Thanks for the advise

Joerg

[jarin]

Hi all, there is a new "switch" for BKGD.
http://jednocipy.kvalitne.cz/osbdm/osbdm-sw2.gif
I used two comparators, one is watching Vdd target level and doesn't allow to charge capacitor unless Vdd voltage is under about 850mV (this can be changed by alternating values of resistors in resistor divider - R1, R2 and R3). Second one is delay circuit and releases BKGD pin after time given by C1 and R5 (and voltage on R2, R3 node) when Vdd is higher than 850mV. It may be good idea to add one more comparator (like Joerg suggested it) with threshold about 300mV switching LED to indicate Vdd falls below LVI rearm value, so that user can see it's the right time to reapply Vdd.
This switch I tested again just with QG8 (in next days I'm going to make test PCB's for other HCS08 families), but in this case it's functionality should not be changed with higher Vdd.

Jarin

[joerg]

Hi jarin
a promised i have had a look at the firmware. The description says that the RESET_IN is the only asynchronous function and this function is a KBD interrupt. I think, since this function is not used by the actual version we can use this function to hold down the BDM data line for a while after the RESET_IN signal has gone LO. So this was the easy part, now i have to get familiar with the firmware (and C ("IGIT"; ugly for a ASM freak)) because the modification may not disturb the USB communication and as i noticed the source code does not work on CW5.x ("only" 51 errors!!). So if somebody has at least done these corrections i would be glad to receive he corrected firmware.

Saluti Joerg

[jarin]

Joerg,
problems about compiling OSBDM firmware was discussed here http://forums.freescale.com/freescale/board/message?board.id=OSBDM08&message.id=217

I also looked to firmware and still do not feel to change it. I like more assembler than C, too.

[joerg]

Hi Jarin
thank for the link, but first the files are no more included in CW5.1 (at least i did not find them) and second we have to bring the project up to date for continuing. The errors are not only due to the old files, rather the compiler has changed the "habit".
i am getting now familiar with the code (and am trying to fix it).

Saluti Joerg

[jarin]

Hi again,

this weekend I've done first "stable" version of my OSBDM. Not very clean work, as you can see on those two pictures
http://www.jednocipy.kvalitne.cz/osbdm/os1.jpg
http://www.jednocipy.kvalitne.cz/osbdm/os2.jpg
I used single-plated board, 1206 sized passive components. Size of PCB is done to fit into particular plastic box.
Schematics is almost the same as I posted before + device with LM393. This is not final version, because I found out placing TVS diode on BKGD line isn't good idea. My OSBDM worked, but somehow "strange". I worked unreliable after bus speed change. When bus speed was above about 8MHz, it showed wrong speeds and above about 14MHz it completely refused to communicate with target. Problem was capacity of this TVS diode (P6KE6V8A) - later I looked into datasheet and it's capacity about 4nF slightly surprised me. I removed this TVS, but I still left the TVS on power pins of target Vdd to protect LVC driver.
On this PCB are still some unnecesary places for components (just for my test purposes) and 3V regulator is maybe slightly hard to find. I'll start to work on new PCB (with more common voltage regulator) and when it will work as I wish, I'll place whole schematics and board layout here.
I know my progress isn't very fast, but it's really only weekend free-time job.

Cheers,
Jarin


/EDITED typos and minor clarifications

Message Edited by jarin on 2007-03-0506:47 PM

[Alban]

Hi Jarin,

Good progress. I don't think someone will argue with the time spent!

Don't hesitate to keep us posted and we'll include your product in the table.

Cheers,

Alban.

[jarin]

Well, I started new thread about subject instead of this long one.
http://forums.freescale.com/freescale/board/message?board.id=OSBDM08&message.id=331&jump=true#M331