Why do I get a NACK when reading the response from the PN7150 device?

[dominusdrr]

Hi.

I'm initializing the PN7150 device with a CORE_RESET_CMD command as shown in the following image:

Then I wait for the IRQ bit to go to logical 1 to try to read the response and I get the following:

It can be seen that a NACK appears in the last byte, so I cannot continue to the next step, which is to obtain the notification.

If you analyze the response frame, it appears to be correct:

0x51 is the control byte where the I2C device address is and the R/W bit is at logical 1 (read)

0x40 is the first byte of the NCI specification and corresponds to the MT value which in this case means response to the previous command

0x00 is the OID and it seems to me that it must be the same value of the sent command.

0x03 is the length of the payload bytes

0x00 corresponds to the Status and means STATUS_OK

0x11 is the NCI Version and I think it means version 1.1

0x01 is the configuration status and the value 0x01 means NCI RF Configuration has been reset

Now if all that is fine, I don't understand why the device generates a NACK. It is similar to reading more bytes than it should.

Any comment or suggestion is welcome.

[dominusdrr · Accepted solution]

I answer to myself.


I'm reviewing the concepts of I2C (learned many years ago) and whoever issues an ACK or a NACK is the one who receives each byte.


In my case, the Microcontroller is reading bytes from the slave, it would be the (MCU) that is issuing a NACK to the PN7150

In the attached image of the logic analyzer, you can see that the IRQ pin goes to logic zero after the last byte, that means that the PN7150 has no more bytes to send to the master. (I think so)

The NACK is to inform the slave not to send any more bytes, the read is finished

I tried to read fewer bytes and the IRQ stays high, I guess it's to report that more bytes still need to be read.

The next step is to read the notification, but it seems to me that this only happens when there was a problem.