Issue with the Waterlevel interrupt

[jayesh_joshi]

Hi,

Let me start by giving some idea about the HIF configuration. Below are connections of PN7462 with the FTDI232 chip.

PN7462  -----------   FTDI232 
  TX        <--------->    RX
  RX        <--------->    TX
GPIO_2  <--------->   CTS
CTS        <--------->   RTS

Now the Waterlevel is configured at 240. and Rx buffer size is 248. When Waterlevel interrupt is generated, GPIO_2 in transit from 0->1. Which will make FTDI232 stop sending data. Now when I transfer 320KB of data I am seeing an overflow error in ErrorCallback. after debugging I found that when I get an overflow error GPIO_2 is low means the Waterlevel interrupt has not been Hit. I have verified the same in debug mode by putting a counter. in Rx callback and Waterlevel callback. I am attaching the HIF section for reference. 

I am also attaching a debug window from which I have driven this conclusion. As you can see when an overflow error has occurred. the Waterlevel hit count() and Rxcallback hit count() are the same it means more than 248 bytes are received but the Waterlevel callback has not been hit and Error callback is called. What could be the reason behind the Waterlevel interrupt not generating. Let me know if more information is required.

Thanks, Jayesh.

[jayesh_joshi]

@Kan_Li  Thanks for the response.

I believe it is Enabled as I am getting the Recieve End callback interrupt. But I am unable to find Register you are referring to. Can you please point out which register or register Bit I have to configure for Enabling HOST_IF? 

Thanks in advance.

Jayesh.

[Kan_Li]

Hi @jayesh_joshi ,

Please kindly check the following register on your side.

Have a great day,
Kan

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[Kan_Li]

Hello @jayesh_joshi ,

Thanks for the information! I have noticed you enable the waterlevel interrupt of HSUART, but didn't find where you enable the Host IF interrupt of NVIC. Would you please clarify? Please kindly refer to the following for more details.

Have a great day,
Kan

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[jayesh_joshi]

Hi @Kan_Li 

I have tried setting HIF Intruppt by adding the below line HIF init API. But still, the issue persists.

/* Enable the Host Interface Input */
PH_REG_SET_BIT(HOSTIF_CONTROL_REG, HIF_ENABLE);

phHal_Nvic_EnableInterrupt( 1<<6 );

Regards Jayesh.

[Kan_Li]

Hi @jayesh_joshi ,

I tried to reproduce your issue here but it works as expected. I built the test code based on phExHif demo, just put phhalHif_ConfigureWaterLevel() right before phhalHif_InitRxBuffer() as described in the API guide.

and the callback was hit right after 1 byte sent out.

You may refer to the API guide or the following for more details.

Hope that helps,

Have a great day,
Kan

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[jayesh_joshi]

@Kan_Li 

Thanks for the response.

You won't be able to see issues in small data transfers. I am facing an issue when I transfer 300kb of data and only 1-2 times waterlevel interrupt is not hitting.  Also, this 300kb of data is going to Reader Writer to Card Emulator device over NFC so there is like NFC data transfer also happening and that could be the reason for waterlevel interrupt not getting generated. Maybe you can help me to debug if that could be the reason.

Regards Jayesh.

[Kan_Li]

Hi @jayesh_joshi ,

Actually it looks like an application issue than a silicon issue, you know, the CLIF interrupt has higher priority than the host IF interrupt, so in some cases when the CLIF interrupt is handling something, the waterlevel interrupt might be set in the same time but the host IF interrupt has to be pending, it is not a good way to set a higher priority for the host IF interrupt, as it might lead to some timing issue from the NFC communication, so better follow the expert's recommendation that I posted in your previous thread: https://community.nxp.com/t5/NFC/How-to-drive-ATX-C-RTS-pin-high-in-PN7462/m-p/1152380#M7662 , Best would be to set the rx buffer size bigger as the expected maximum frame size. Multipe rx buffers can be used to operate in a parallel way. 

Have a great day,
Kan

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