Would be grateful if anyone can figure out why ANTFAIL bit is set.
The hardware Ra=15R La=800uH Ca=2nF Cs=100nF Rl=1k combination was proven work on other design, we are only having a board respin.
Oscilliscope looks fine on Tap point and Voltage RX Pin lower than DLEV -1.18V?
Anyone have clue what might be the problem?
Also on the application note AN98080 example shown below
I was plugging Rin = 32 Ra = 2 La=20uH w=125khz following example,
and absolutely could not get the C1=23.3nF C2=62.4nF result below.
Further math explaination/calculations would be apprecitated.
Best regards.
已解决! 转到解答。
On the first problem, turns out to be a configuration problem on my end, silly mistake.
On the second one, turns out w = 2pi*f ...... I don't know why but it never hit me that w is cycle per unit per time.
On the first problem, turns out to be a configuration problem on my end, silly mistake.
On the second one, turns out w = 2pi*f ...... I don't know why but it never hit me that w is cycle per unit per time.
Hello sir,
I'm very sorry but, could you please be a little more specific on the issue you are having with your application design? What do you mean by "having a board Respin"?
Regarding the values of C1 and C2. I will have to request this information from the expert since there isn't another document that deepens into the math calculations.
Could you please let me know if you have a schematic or PCB where you are simulating or physically measuring the antenna with a VNA?