Dear Naoki Okazaki,
Hope you are doing great, We would actually expect the same ESD behavior between the “old” and the “new” design. There are a lot of environmental factors in the assembly process that influence the ESD stress on the IC (pick & place tool, rolls, tilt, ….). To get a better understanding for the different yield you would need to do read outs after each step of the assembly process for the “old” and “new” design. We assume, that you have a proof point (curve trace), that the yield difference is based on ESD.
BR
Jonathan