I have encountered two issues relating to the SPI clock on a S32K344 when integrating with an ADE7912.
- There is an undesired leading pulse on the SPI clock causing a bit-shift, corrupting the data.
- I am unable to resolve this issue by delaying the chip select, as the chip select is on a MUX IC and controlled through GPIO. I have attached my SPI configuration from the S32 configuration tool, and the output from a logic analyzer.
- The clock duty cycle is not fixed at 50% when at high speeds. At 4MHz, the duty cycle of the clock is around 65% which does not meet the timing requirements of the selected SPI device. Lowering the SPI clock speed to 2MHz results in a duty cycle of 58%. Please advise how to ensure a 50% duty cycle at 4MHz.
Any advise for resolving these issues would be appreciated.
Hi,
1) seems the behavior you see is due to driver implementation of a workaround for errata 0050456, when module reset is used. This puts clock pulse and sets SOUT high until data is transmitted. This is not an issue for slave devices if really controlled by CS and SCK, but for usage you have it would bring issue.
Try to do not use module reset and keep resetting the FIFO using CR[RTF] and CR[RRF]
2) this can be issue of the analyzer sample rate, but also for higher rates, try to increase pins drive strength.
3) to read more bytes from slave you need to send required dummy bytes from master keeping CS selected.
BR, Petr
