how to init the watchdog for MPC5748G

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how to init the watchdog for MPC5748G

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happy_larry
Contributor II

Hi everyone,

 

I'm trying to devolopment the bootloader for MPC5748G, we meet a problme about the watchdog.

 

We have used the default project configuration of S32 V1.0 for power, and we changes nothing for the interrupt vector table.

Then we used the below code to init the watchdog after call the xcptn_xmpl. When we want to write the specifed value into SWT, err will occurs. Acturally, both read and write of the SWT register will cause the err. The CPU will go to IVOR1_Vector. We have checked that the pointer to the SWT is correct. SWT_0 is start from 0xFC050000 and the SWT_0.SR is 0xFC050010.

 

Can anyone know how to init the watchdog or help me to solve the problem?

 

 

void Wdg_Init(void)

{

while(MC_ME.GS.B.S_SIRCON != 1U)

{

/* SWT must be configured only if the 128 KHz internal

        RC oscillator is providing a stable clock */

}

 

SWT_0.SR.R = 0xC520U;       /* error occurs here, CPU will go to IVOR1_Vector.*/

SWT_0.SR.R = 0xD928U;      

 

/* WDG can only be serviced with fixed sequence */

SWT_0.CR.B.SMD = 0U;

 

/* Generate a reset on a time-out */

SWT_0.CR.B.ITR = 0U;

 

    /* Invalid access to the SWT causes a system reset */

SWT_0.CR.B.RIA = 1U;

 

/* SWT continues to run in stop mode */

SWT_0.CR.B.FRZ = 1U;

 

/* SWT continues to run in stop mode */

SWT_0.CR.B.STP = 0U;

 

/* Set time-out clock cycles */

SWT_0.TO.R = WDG_TIMEOUT_VALUE;

 

/* SWT enabled */

SWT_0.CR.B.WEN = 1U;

 

/* Make the WDG enter soft lock mode */

SWT_0.CR.B.SLK = 1U;

}

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1 Solution
1,589 Views
martin_kovar
NXP Employee
NXP Employee

Hi,

this problem becomes, because during startup, core access to SWT is disabled (this is the IVOR1 reason).

Look at the startup code (section Turn off SWTs) and update the last three lines with the following code:

e_lis    r3, 0xFF00

e_or2i    r3, 0x010A

e_stw    r3, 0(r4)

Now you should be able to configure SWT.

Regards,

Martin

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3 Replies
1,589 Views
alexvinchev
Contributor V

Hi,

can  you try this code:

;SWT_0.SR.R = 0xc520;
e_lis      r12, -0x3FB
e_li       r0,  0xC520
e_li       r11, 0xD928
;SWT_0.SR.R = 0xd928;
e_stw      r0,  0x10(r12)  # r0,16(r12)
e_lis      r0,  -0x1000
e_stw      r11, 0x10(r12)  # r11,16(r12)
;SWT_0.CR.R = 0xFF00010A;
e_add16i   r0,r0,0x10A
e_stw      r0,  0x0(r12)   # r0,0(r12)

Add it as close as possible to your start point (before ECC RAM init). This code disables the STW0, but in your case will prove that you can or you can not write to SWT_0.SR.R.

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happy_larry
Contributor II

Thanks very much for you replay!

I will try your solution.

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1,590 Views
martin_kovar
NXP Employee
NXP Employee

Hi,

this problem becomes, because during startup, core access to SWT is disabled (this is the IVOR1 reason).

Look at the startup code (section Turn off SWTs) and update the last three lines with the following code:

e_lis    r3, 0xFF00

e_or2i    r3, 0x010A

e_stw    r3, 0(r4)

Now you should be able to configure SWT.

Regards,

Martin