eQADC and SW-triggered conversions

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eQADC and SW-triggered conversions

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NXP Employee
NXP Employee

Hi,

I am facing a weird behaviour of the eQADC module, when triggerering a conversion by SW: a CFIFO underflow is reported (FISR[CFUF]) , whereas I filled the CFIFO just before launching the conversion, with the last command having the EOQ bit set.

I am suspiscious about the way I generate the SW trigger: I write the SSE (SW trigger) bit and the MODEx field (selection of SW trigger single scan) of the register CFCR in the same instruction. The issue tends to disappear when I use two instructions to write each bit field. However I could not find any note in the RM that could back-up this hypothesis.

So should the CFCR[SSE] bit be written to individually to launch a SW triggered conversion ?

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NXP TechSupport
NXP TechSupport

Hi, SSE bit and the MODEx is possible to write at once by
EQADC_A.CFCR[0].R=0x0410

See my example here where I am doing it just this way and it works fine:

https://community.nxp.com/docs/DOC-105723 

View solution in original post

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66 Views
NXP TechSupport
NXP TechSupport

Hi, SSE bit and the MODEx is possible to write at once by
EQADC_A.CFCR[0].R=0x0410

See my example here where I am doing it just this way and it works fine:

https://community.nxp.com/docs/DOC-105723 

View solution in original post