I am facing a weird behaviour of the eQADC module, when triggerering a conversion by SW: a CFIFO underflow is reported (FISR[CFUF]) , whereas I filled the CFIFO just before launching the conversion, with the last command having the EOQ bit set.
I am suspiscious about the way I generate the SW trigger: I write the SSE (SW trigger) bit and the MODEx field (selection of SW trigger single scan) of the register CFCR in the same instruction. The issue tends to disappear when I use two instructions to write each bit field. However I could not find any note in the RM that could back-up this hypothesis.
So should the CFCR[SSE] bit be written to individually to launch a SW triggered conversion ?
Solved! Go to Solution.