Hi, I'm using MPC5676R with trace32,
The example code "XPC567XRKIT-PinToggleStationery-V0_7" has optimization.c and optimization.h files.
when OPTIMIZATIONS_ON = 1 , Optimizations() function will be executed to enable cache.
but, When I call the MMUSRAMIsCacheable(), the operation is weird.
I can't change any member variables of struct, but other global variables can be changed in trace32 WATCH window.
I thought that the code in MMUSRAMIsCacheable() function is wrong, but I don't know what it does mean.
In AN4324, the SRAM code is different with the example MMUSRAMsCacheable() code.
When I change the code according to AN4324, It does not affect.
What is the reason about these phenomenon?
- does the write access fail while core running, halted or both?
- how does it fail? E.g. error message?
- is macro DCACHE_COPYBACK_MODE also set?
- what is the address of the failing access?
-The write access is successful when core is halted, but not running.
so I have to pause to change values
- It dose not alert error message
- DCACHE_COPYBACK_MODE is disabled, it must be write through method
- How can I see the address of the access?
Please try with
SYStem.Option NexusMemoryCoherency ON
On MPC5676R and MPC5777C, this setting willconfigure the debugger to tell the CCU that the caches have to be snooped for this the memory access. This setting is only allowed if the processor is configured to write-through mode, like in your case.
Thank you for your response!
But It does not work.
The command button does not appear in system window and I cannot think it was taken effect
when I input the command in command window.
Hi, I just checked it and I don't see any issue.
I guess it could have something to do with access class attributes in the TRACE32 setting. Try to investigate
If you show me specific case when the issue happens I could try it here.