Hi,
Is ECC algorithm for SRAM , applied to whole memory region or just dedicated memory space for this test.
1. ECC mechanism is used on whole SRAM.
If they are applied to whole memory, how to manage data changes in SRAM? Variable changes are written with their new error bits?
2. On every write there is a new syndrome written along with data.
If I change an area in SRAM during debug session, this change isn't perceived as ECC error by the microcontroller, Why? Especially, I need to know that,
3. Debugger write to SRAM via SRAM controller where the ECC syndrome is generated and stored in SRAM array.
If there is one or more bit change(caused by radiation, electro-magnetic interference, or electrical noise) in any region of SRAM, will ecc detect this error?
4. Yes, ECC mechanism will detect that stored data+syndrome are different from the one read by controller. This is how the ECC works in general.
In generally, how does ECC work?
5.Would be good to read for example AN where it is already explained or some general documentation like reference manual.
https://www.nxp.com/docs/en/application-note/AN5200.pdf?fsrch=1&sr=1&pageNum=1
Peter
