Question about UTEST Secure boot configuration with DCF clients on MPC5777C

[Zhongling_Lang]

Hi team,

Customer have issue with secure boot which showing system memory error in CSE_ECR register on MPC5777C occasionally and the secure boot failed.

So we check the AN5418 which said the CSE and boot code may be interfere with each other in parallel mode.

So customer want to run sequential secure boot mode with DCF configuration, but the RM show that it only can configure by NXP(write_once), So question is why it have this restriction? and how to resolve this issue in customer boot code, the AN just said set CSE_CR[SUS] to 1.

[lukaszadrapa]

Hi @Zhongling_Lang 

yes, the DCF record is write-once only and it cannot be changed by user. It's configured to parallel mode.

The CSE reads the flash in parallel to running application code, so application code should not configure the flash at this moment (like configuring wait states or prefetching...) and it should not start other flash operations (program/erase, flash array integrity check...). Workaround is to read the CSE status register to check if the secure boot is already finished and then you can safely run such operations. Or, as mentioned in your screenshot, suspend the secure boot, perform the flash configuration and resume the secure boot.

Regards,

Lukas