Hello,
I am trying to put MCP5675K into debug mode but I am failing to do so.
I am using OpenOCD with FT2232H with custom scripting. This is based on this patch.
TRST is connected to JCOMP, SRST to chip reset (RESET_B).
I am able to see correct JTAG ID and OnCE ID.
I am trying based on AN4356 as it says:
1. Assert RESET.
2. Set the OCR[DR] and OCR[WKUP] bits.
3. Deassert RESET.
4. Verify debug mode via the DEBUG bit in the OnCE status register.
5. Clear the OCR[DR] bit while leaving OCR[WKUP] set and set OCR[FDB].
When I set those bits, it never gets reflected in OSR (OnCE status register). I am only able to get 0x201 or 0x241 value. Never seen 0x209. This is my output:
$ ./openocd/src/openocd -f spc.cfg
Open On-Chip Debugger 0.11.0+dev-00059-g56506d2ed (2024-01-26-00:37)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
DEPRECATED! use 'adapter speed' not 'adapter_khz'
Info : clock speed 2000 kHz
Info : JTAG tap: mcp5675.cpu tap/device found: 0x0aec101d (mfg: 0x00e (Freescale (Motorola)), part: 0xaec1, ver: 0x0)
Warn : gdb services need one or more targets defined
Sending IDCODE command
IDCODE: 0aec101d
Info : JTAG tap: mcp5675.once enabled
Info : JTAG tap: mcp5675.cpu disabled
OnCE JTAG ID = 0x07e2f01d shall be 07e2f01d
OSR = 0x0241
Enter debug mode...
asserted
ocr set
OSR = 0x0241
deasserted
OSR = 0x0201
OSR = 0x0201
OSR = 0x0201
OSR = 0x0201
OSR = 0x0201
OSR = 0x0201
My questions:
- Do you see something obvious what am I doing wrong?
- What is meant by RESET? JCOMP or chip reset?
- Is is possible the chip is in censored mode? How can I check?
