QSPI Peripheral reading Support

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QSPI Peripheral reading Support

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enggmahesh84
Contributor I

Hi 

I am Using QSPI in MPC5606s micro.

The register used to enable QUAD read and 4 byte burst[QUADSPI_0.ACR.R = 0x00A040EB;]

if I set the above register,I cannot able to read the data sequentially.

4 byte burst is enabled after setting the above register,

First & second bytes are missing, third & four bytes able to read,fifth & six bytes are missing it is going on

Thanks

Mahesh

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enggmahesh84
Contributor I

Thanks David for your support..!

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enggmahesh84
Contributor I

In My Controller(MPC5606S) LCR register is not avaliable..only ACR register is Present

After setting the register QUADSPI_0.ACR.R = 0x00A040eb;  

if I try to take memory dump, First data shifted 4bytes right.

Please suggest any other steps to read the data from QUADSPI..

Please share any sample code for S25FL064L(Manufacture->Cypress) if available..

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davidtosenovjan
NXP TechSupport
NXP TechSupport

I am sorry, it was taken from example for MPC5645S, my fault.

Below you may find initialization code for MPC5606S and S25FL064P device. Possible differences between S25FL064P and S25FL064L please consult with Cypress:

https://www.cypress.com/ 

#define qspi_wait_for_ICR_complete()     while(QUADSPI_0.SFMSR.B.BUSY)
#define qspi_get_receive_data()     (*(vuint32_t *)(0x87FFFFFC));

#ifdef SPECTRUM
void QSPI_Init( void  )
{

  uint32_t qspi_rx_data;
  SIU.PCR[PF10].R = 0x0A03;
  SIU.PCR[PF11].R = 0x0B03;
  SIU.PCR[PF12].R = 0x0203;
  SIU.GPDO[PF12].B.PDO = 1;
  SIU.PCR[PF13].R = 0x0703;
  SIU.PCR[PF14].R = 0x0703;
  SIU.PCR[PF15].R = 0x0603;
 
  CGM.AC3_SC.B.SELCTL = 1;      //set QSPI clock as sysclk/2


  QUADSPI_0.MCR.R = 0x00000088;

  QUADSPI_0.ICR.R = 0x00010035;
  qspi_wait_for_ICR_complete();
  qspi_rx_data = qspi_get_receive_data();

  if ((qspi_rx_data & 0xFF000000uL) != 0x02000000uL)
  {

    SIU.PCR[PF11].R = 0x0203;
    SIU.GPDO[PF11].B.PDO = 1;


    QUADSPI_0.ICR.R = 0x00000006;
    qspi_wait_for_ICR_complete();


    QUADSPI_0.TBDR = 0x00020000;
    QUADSPI_0.ICR.R = 0x00020001;
    qspi_wait_for_ICR_complete();


    SIU.PCR[PF11].R = 0x0B03;
  }


  SIU.PCR[PF12].R = 0x0B03;

  QUADSPI_0.ACR.R = 0x000040EB;
}
#else

Hope it helps

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davidtosenovjan
NXP TechSupport
NXP TechSupport

Hi, I was checked some example code, where following setting has been shown:

    #if QUAD_READ == 1
        /* enable quad reads */
        QUADSPI_0.LCR.R = 0x4;             /* set LCR to 4 dummy cycles. Required for Spansion. */
        QUADSPI_0.ACR.R = 0x00A080eb;     /* Use Quad I/O reads - Command: 0xEB, Read Size:128bytes */
    #endif

Do you have it so?

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