PXS3020 RANDOM BOOT UP ISSUE

[rameshmarichamy]

Hi

I am using PXS3020 series micro controller in one of my application. I am operating it in external VREG mode.

The delay between 3.3V HV IO and 1.2V LV voltages is almost 6-10ms. (3.3V comes first and 1.2V is delivered later)Attached image for your reference.

I am driving the RESET_SUP pin (Pin no.AC20) using a open drain buffer which is reset by an external reset source. I have a pull up at open drain buffer output to 3.3V. Since my 3.3V rises first, the RESET_SUP releases before 1.2V.

I have around 5 modules which is working fine without any issues. But one of the module boots randomly during power up.

While debugging , I could see a statement in the datasheet that RESET_SUP not be released unless VDD_LV_xxx is within its valid range of operation. But the micro controller core starts working only after all voltage rails are up.

Will this could be the reason? what is the tech. reason for the statement. if RESET_SUP could be issue, why my other modules didn't have any issues so far past 2 years.

Please assist me in resolving the issue.

Regards,

Ramesh.M

I am using PXS3020 series micro controller in one of my application. I am operating it in external VREG mode.

The delay between 3.3V HV IO and 1.2V LV voltages is almost 6-10ms. (3.3V comes first and 1.2V is delivered later)Attached image for your reference.

I am driving the RESET_SUP pin (Pin no.AC20) using a open drain buffer which is reset by an external reset source. I have a pull up at open drain buffer output to 3.3V.

Since my 3.3V rises first, the RESET_SUP releases 6-8ms before 1.2V.

I have around 5 modules which is working fine without any issues even during extreme ambient temperatures. But one of the module boots randomly during power up.

While debugging , I could see a statement in the datasheet that RESET_SUP not to be released unless VDD_LV_xxx is within its valid range of operation. what is the tech. reason for the statement?.

If RESET_SUP could be issue, why my other modules didn't have any issues. is there a chance for the modules to work by not following the above condition?.

Please could you explain me is there by any chance the controller can be made working without this reset_sup?. Also could you brief how it could have worked so far?

Though theoretically the sequencing conditions are not met, practically it is working without any issues even during extreme ambient temperatures.

Please assist me in resolving the issue.

I have attached the image for your reference.

Regards,

Ramesh.M###@

[lukaszadrapa]

Hi,

yes, the RESET_SUP_B must be asserted if the core voltage is not within specified range. It can't be deasserted earlier. See the attached presentation, there are a lot of recommendations related to power supply. There are also the same notes about the RESET_SUP_B.

Regards,

Lukas

[rameshmarichamy]

Hi Lukas,

Yes its agreed RESET_SUP# needs to be released after 1.2V Core voltage stabilises.

As recommended i have used open drain type buffer with a pullup to drive this pin from a external reset generator.

In my case few modules are working fine without issues (RESET_SUP#) Released 5ms before 1.2V core.

Since we do not have any chip level specs. and just a recommendation, I request whether could you explain what could be the reason for working? (based on chip level sequencing test results in house).

Regards,

Ramesh.M

--- Original Message

[lukaszadrapa]

Hi Ramesh,

the microcontrollers are thoroughly tested in given operating conditions, so we can guarantee the functionality if the devices are operated within this specification. Of course, the device can work also outside the spec but we can't guarantee that it will work and we do not test it.

Regards,

Lukas