MPU core1 mpc5777C

[Othmane1]

Hi,

I'm using MPC5777C evaluation board to test the MPU on core1, i created a section in core1 where only read is allowed for core1 and i was trying to write into one memory region inside that section and it did actually allow me when it was supposed to not allow!!!

also when i try to define a section in core0 RAM and give only read access to core1 this time when i try to write from core1 it prevents me so I'm confused is MPU only allowing us to prevent other BUS masters that is outside the RAM area of the current BUS master?

#define CPU1_CPU0_SHARED_DATA_START_ADDRESS                    0x40070000u

#define CPU1_CPU0_SHARED_DATA_END_ADDRESS                      0x4007FFFFu

#define CORE0_SUPERVISOR_MODE_ACCESS(x)                        MPU_RGD_WORD2_M0SM(x)

#define CORE0_USER_MODE_ACCESS(x)                              MPU_RGD_WORD2_M0UM(x)

 

#define M3UM_USER_MODE_READ_ALLOWED                            0x4u

#define M3UM_USER_MODE_WRITE_ALLOWED                           0x2u

#define M3UM_USER_MODE_EXECUTE_ALLOWED                         0x1u

#define M3UM_USER_MODE_READ_AND_EXECUTE_ALLOWED                0x5u

#define M3UM_USER_MODE_ALL_ALLOWED                             0x7u

    /* RAM: CPU1->CPU0 shared data */

    MPU_0->RGD[4].WORD0 = CPU1_CPU0_SHARED_DATA_START_ADDRESS;  /* Start address */

    MPU_0->RGD[4].WORD1 = CPU1_CPU0_SHARED_DATA_END_ADDRESS;  /* End address */

    MPU_0->RGD[4].WORD2 = CORE0_SUPERVISOR_MODE_ACCESS(M3SM_SAME_AS_USER_MODE_DEFINED_IN_M3UM);

    MPU_0->RGD[4].WORD2 |= CORE0_USER_MODE_ACCESS(M3UM_USER_MODE_READ_ALLOWED); /* only read and execute is given since it is overlapping region*/

    MPU_0->RGD[4].WORD2 |= CORE1_SUPERVISOR_MODE_ACCESS(M3SM_SAME_AS_USER_MODE_DEFINED_IN_M3UM);

    MPU_0->RGD[4].WORD2 |= CORE1_USER_MODE_ACCESS(M3UM_USER_MODE_READ_ALLOWED);/* only read and execute is given since it is overlapping region*/

    MPU_0->RGD[4].WORD2 |= CORE1_PID_IS_INCLUDED(1);

    MPU_0->RGD[4].WORD2 |= SIPI_WRITE_ACCESS(BUS_MASTER_ACCESS_ALLOWED);

    MPU_0->RGD[4].WORD2 |= SIPI_READ_ACCESS(BUS_MASTER_ACCESS_ALLOWED);

    MPU_0->RGD[4].WORD3 = REGION_DESCRIPTOR_IS_VALID;  /* Mark descriptor as valid */

    MPU_0->RGD[4].WORD3 |= MPU_RGD_WORD3_PID(0x1);

   MPU_0->CESR = MPU_CESR_VLD(1); /* Enable MPU */

PS: I'm only using MPU_0 instance 

[davidtosenovjan]

MPU0 can only protect PRAMC_0 (means address range 0x40000000–0x4003FFFF)
MPU1 can only protect PRAMC_1 (means address range 0x40040000–0x4007FFFF)

That's probably the point.

[Othmane1]

Hi,

Exactly i did just realized that, but now i have another problem, which is whenever i enable the MPU_1 without giving write access to the first 64 KB of the PRAMC_1 i always end up in the IVOR1, and my tasks are in that range, because my goal is to create tasks each with a specific PID then whenever i initiate a task i configure the an MPU region (overlapping with the first region) with what that tasks need to read/write but the problem is that these variable that these tasks needs to read are in that first 64kB and in there, everything is already allowed (read/write) so it is kind of the MPU always considering the permissions in the first region.

PS1: I don't enable PID for core1 in the configuration of the first region, but i do that for the tasks regions 

PS2: My main goal goal is that for every task created it shall have only access to it stack unless otherwise given access to a specific variale 

[davidtosenovjan]

I am not sure if I understand your update completely, but overlapping MPU region lead in granting permission if there is a conflict in the setup.