Use Case: To Remap the Calibration Region
Tools: Lauterbach Debugger
Target: MPC5777M Microcontroller
Calibration: ENGINE_01_Calibration [Address: 0x09457E99--0x09457E99]
Description:
We would like to Remap the Calibration region and got information from the MPC5777M reference Manual that we should use “PFlash Calibration Remap Descriptor Enable Register (PFCRDE)”. We would like to use either
Extended Overlay RAM [Address: 0x0C000000 0x0C1FFFFF and Size: 2 MB]
OR
Internal Overlay RAM [Address: 0x0D000000 0x0D003FFF and Size: 16 KB]
Source: https://www.nxp.com/files-static/32bit/doc/ref_manual/MPC5777MRM.pdf (Page: 164)
Steps Followed to Remap the Calibration ENGINE_01_Calibration [Address: 0x09457E99--0x09457E99] using PFlash Calibration Remap Descriptor Enable Register (PFCRDE):
1. Enable Calibration Remap Descriptor 0,1,2 == 01
2. Platform Flash Calibration Region Descriptor n Word0 (PFLASH_PFCRDn_Word0):
While setting this PFLASH_PFCRDn_Word0, we are not sure about the “LSTARTADDR” which needs to be specified to configure the descriptors.
Address: 0h base + 100h offset + (16d × i), where i=0d to 31d
Similarly, we are also unclear about the address, which needs to be set to configure the PFLASH_PFCRDn_Word1 & PFLASH_PFCRDn_Word2.
3. Platform Flash Calibration Region Descriptor n Word1 (PFLASH_PFCRDn_Word1):
4. Platform Flash Calibration Region Descriptor n Word2 (PFLASH_PFCRDn_Word2):
5. Enabled global remap enable PFCRCR[GRMEN] == 01
Regards,
Dhanesh.
Hi,
you can check this example:
Example MPC5748G Overlay SRAM Overlay Flash config S32DS
There's a function:
void Overlay(uint32_t word0, uint32_t word1, uint32_t word2, uint32_t descriptor)
{
PFLASH.PFCRD[descriptor].Word0.R = word0; /* Logical address */
PFLASH.PFCRD[descriptor].Word1.R = word1; /* Physical address */
PFLASH.PFCRD[descriptor].Word2.R = word2; /* Enable remapping for individual masters, size of page */
PFLASH.PFCRDE.R |= (uint32_t)0x80000000 >> descriptor; /* Enable descriptor */
PFLASH.PFCRCR.B.GRMEN = 1; /* Global Remap Enable */
}
And here is an example how to overlay flash at 0x09457E80 by SRAM at 0x0D000000:
Overlay(0x09457E80, 0x0D000000, 0xFFFF0007, 1);
In this case, I used descriptor size (CRDSize) 128 bytes. That means the address must be aligned to 128 bytes. You can use address 0x09457E99. Smallest region size is 32 bytes, so the address must be aligned to 32bytes too.
Regards,
Lukas
Hi Lukas,
Thanks for your quick reply,
I am already following your example code which you posted on another topic.
I just followed the steps described by you and it didn't work.
- PFLASH.PFCRD[descriptor].Word0.R = 0x09457E80
- PFLASH.PFCRD[descriptor].Word1.R = 0x0D000000
- PFLASH.PFCRD[descriptor].Word2.R = 0xFFFF0007
- PFLASH.PFCRDE.R == 0x80000000
- PFLASH.PFCRCR.B.GRMEN = 01
Also tried with Overlay(0x09457E99, 0x0D000000, 0xFFFF0005, 1), it too din't work.
I also noted in your main.c code that you had enabled some peripherals, Do I need to set all these?
Regards,
Dhanesh.
Hi Dhanesh,
it's just a typo:
Address of overlay SRAM is not 0xD000_0000 but 0x0D00_0000.
Regards,
Lukas
Hi Lukas,
I am trying to set the PFCRD0_WORD0 & PFCRD0_WORD1 there is >> 4-bit shifting is happening, but I couldn't able to see this behavior in your screenshot.(
Actually I am writing 0x0D000000 but >> 4-bit Shifting is happening and it takes 0XD0000000.
Hi,
PSTARTADDR is a bit field where last four bit of address are not visible.
The debugger shows content of whole 32bit register on the left side and content of bit field on the right side. That's the reason why it is "shifted".
When you write to whole Word1 register, it should be:
PFLASH.PFCRD[n].Word1.R = 0x0D000000;
If you write only to bit field:
PFLASH.PFCRD[n].Word1.B.PSTARTADDR = 0x0D00000;
Regards,
Lukas
