MPC5777C - Ensuring that core 1 clock source is equal to zero

[MatheusFranklin]

Hello!

I need to guarantee that the core 1 is completely disabled. The core reference manual (e200Z759N3CRM) names the input clock source of the core as "m_clk".

The MPC5777CRM says that, when in reset state, the core clock is "stopped".

I need to confirm if the "m_clk" of the core is gated off when in reset state.

Thanks, 

Matheus

[petervlna · Accepted solution]

Hello,

Yes in reset state the clocks are gated. So if you have just one core in reset the clock will be gated to that particular core.

Not sure what is m_clk signal you have mentioned , but the cores are supplied by core_clk

Best regards,

Peter