In this chip, we have four ADC engines, I calibrated all four ADC engines by reading and calculating OCC and Gcc registers.
However, when I test it, only EQADCA unit 0 is accurate, all other three unit is not accurate.
For example:
I feed 5V to both EQADCA 0 and eQADCA1, the channel in unit 0 shows 4.95v, however, the channel in unit 1 shows me only 3.98v after scaling.
I did exactly the same configuration to all the ADC units.
Any suggestions?
Thanks a lot
Hi, it is huge error, thus I would rather see some SW error or reading of wrong channel (result swap issue) or something similar. Try to check following document:
https://community.nxp.com/docs/DOC-329779
Regarding calibration I would like to note several points:
- there are 8 pairs of OCC/GCC registers - there are 2 eQADC modules, both consists of 2 ADC units and every has OCCR/GCCR (for standard conversion) and AOR/AGR (for alternate conversions)
- user SW must ensure that reference channels are not converted simultaneously by 2 ADC modules (guaranteed by proper ordering in the command queues)
- Sampling of reference channels is always supposed to be converted without CAL bit set.
- Normal conversions after calibration are supposed to be converted with CAL bit set.
In other aspect I would link to AN2989, describing calibration procedure in great detail:
https://www.nxp.com/docs/en/application-note/AN2989.pdf
If you have your own prototype board, I would pay attention to REFBYPC lines to check whether all 4 lines has connected external capacitor there. Our EVB has it connected properly.
Hello, thanks for the response.
I am using multiple command queues and multiple result queues, and they are match to each other.
For example:
For the command enter CFIFO 0, will have the results go to RFIFO 0.
So I don't think it is the wrong channels issues.
And even without calibration, the results should not be deviate that much.
I am using NXP EVB for pre-development.
Let me describe the issue in more detail:
I am testing all four ADC units, I will show an example:
1. CFIFO 0 in eQADCA 0, result will go to RFIFO 0.
2. CFIFO 1 in eQADCA 1, result will go to RFIFO 1.
3. CFIFO 0 in eQADCB 0, result will go to RFIFO 0.
4. CFIFO 1 in eQADCB 1, result will go to RFIFO 1.
I assigned three ADC channels for each CFIFO, all the 12 channels are different.
All the four FIFOs will be triggered by the same hardware trigger signals.
That means they will be triggered at the same time.
The problem is:
If I only configure step 1, or only configure step 2, I can have the precise answers.
However, if I configure all the 4 steps, when comes to 5V input rest voltage, only answers that goes into eQADCA RFIFO0 are correct, all the three RFIFOs are way below 5V.
When comes to low input voltages, like 1.25V or 3.3V input, all four RFIFOs can give me reasonable values.
Any comments on that?
Thanks a lot for your help
Hello David
I figured out the problem, it is a clock configuration issue, I am using NXP AUTOSAR MCAL ADC module, and the generated code had an incorrect clock configuration.
I manually changed the generated code and change the wrong clock configuration back, it is working properly. I will report this issue to the NXP AUTOSAR MCAL team.
Thanks a lot for your help
I really appreciate it.