MPC574xG FS80 clock limitation related to SPI data

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MPC574xG FS80 clock limitation related to SPI data

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namnguyenviet
NXP Employee
NXP Employee

Hello guys,

Currently I have been struggled with a strange issue: I have configured a SPI master in DSPI_0/SPI_0, however whenever the SPI master send the data, data is duplicated in two first bytes (e.g. 0x1, 0x1, 0x3, 0x3, 0x5, 0x6 instead of 0x1, 0x2, 0x3, 0x4, 0x5, 0x6).  All the DSPI settings seems to be correct, and I have gone through all the MC_CGM settings, they are looked good however I realized the FS80 clock frequency is the issue, as I can see the issue is gone when FS80 is increased from 20MHz to 40MHz, although FS80 is not related to DSPI clock source.

Is there any reasonable explanation for this case? Here is my clock tree:

System Clock using PLL source, at 160MHz. PLL chooses XOSC as clock input.

MC_CGM settings:

MC_CGM_SC_DC0[DIV] = 0: S160 = 160Mhz

MC_CGM_SC_DC1[DIV] = 1: S80 = 80Mhz

MC_CGM_SC_DC2[DIV] = 3: S40 = 40Mhz

MC_CGM_SC_DC3[DIV] = 3: F40 = 40Mhz

MC_CGM_SC_DC4[DIV] = 1: F80 = 80Mhz

MC_CGM_SC_DC5[DIV] = 7: FS80 = 20Mhz (increased to 40Mhz in order to get rid of the issue)

MC_CGM_SC_DC6[DIV] = 7: F20 = 20MHz

Best Regards,

Nam

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1 Solution
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PetrS
NXP TechSupport
NXP TechSupport

Hi,

most probably this is due to PBRIDGE that is clocked at FS80, also other modules is running at that clock like DMA, INTC...
RM states that FS80 cannot be lower that 40MHz.

PetrS_1-1613735633344.png

 

PetrS_2-1613735837029.png

 

BR, Petr

 

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1 Reply
578 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi,

most probably this is due to PBRIDGE that is clocked at FS80, also other modules is running at that clock like DMA, INTC...
RM states that FS80 cannot be lower that 40MHz.

PetrS_1-1613735633344.png

 

PetrS_2-1613735837029.png

 

BR, Petr