Hello,
I've been developing on the MPC5748G MCU in S32DS using the SDK 3.0.0 and I discovered that for any port other than PTA (PTB, ..., PTQ) the pointer to their MPGPDO register is at the wrong address. You can see this from the helper struct here:
/** GPIO - Register Layout Typedef */
typedef struct __attribute((packed)) {
__IO uint16_t PGPDO; /**< SIUL2 Parallel GPIO Pad Data Out Register, array offset: 0x1700, array step: 0x2 */
uint16_t RESERVED_PGPDO[SIUL2_PGPDO_COUNT - 1U];
__I uint16_t PGPDI; /**< SIUL2 Parallel GPIO Pad Data In Register, array offset: 0x1740, array step: 0x2 */
uint16_t RESERVED_PGPDI[SIUL2_PGPDI_COUNT - 1U];
__O uint32_t MPGPDO; /**< SIUL2 Masked Parallel GPIO Pad Data Out Register, array offset: 0x1780, array step: 0x4 */
} GPIO_Type;
Say you want to access PTI->MPGPDO (in the SIUL2 this would be SIUL2->MPGPDO[8]). PTI and therefore PTI->PGPDO starts at 0xFFFC_1710 and then you travel down the struct 31x2 bytes to get to PTI->PGPDI. However, to get to PTI->MPGPDO, you'd have to travel (32-8)*2bytes + 7*4bytes instead of 32x2bytes.
I unfortunately cannot see a way to solving this problem on the GPIO_Type level, however a workaround is to use the SIUL2 registers directly as:
// Sets a pin with an atomic operation
void Pin_AtomicSet(GPIO_Type *const port, const uint32_t pinIdx, const bool val){
const uint32_t mask = 1ull << (15-pinIdx);
const uint32_t mppdo = val ? mask : 0;
const uint32_t portIdx = ((uint32_t)port - (uint32_t)PTA_BASE)/2;
SIUL2->MPGPDO[portIdx] = (uint32_t)(SIUL2_MPGPDO_MASK(mask) | mppdo);
}
