Hello NXP:
I use MPC5674F EBI, the burst mode on CS0. Can the Pipelined SRAM (with NoBL) be used? The SSRAM is CY7C1370KVE33.
Our reference designs always contain Flow-through memories. However MPC55xx/56xx is capable of interfacing with SRAMs that operate in either Flow Through or Pipeline mode that is usable with the addition of wait states in the MCU’s read timing.
I could recommend you to see following third party document dealing with this topic:
ok , thanks