Could not reset / or attach MPC5748G in trace32 using JTAG debugger

[chfakhtchfakht]

HI everyone,

I am using MPC5748G processor for a certain application and using Trace32 Lauterbach for debugging and flashing. My problem is that when my application resets the core multiple times, the processor goes in a state where it has to be power-cycled, and simply resting the target doesn't work.

meanwhile the debugger lists this error message :

"    system.up error: received invalid OSR (0x000)

                                - does the target assert JCOMP while RESET is asserted?

                                - is the device censored?

     error: received invalid OSR while core running (0x000) "

I have tried :Tools - Halt core at power-on reset.  But there is no cmm file found for this

so is it a hardware limitation or is there any script that can help me solve this problem ?

Looking forward reply,

[lukaszadrapa]

Hi,

it is caused by reset escalation feature:

The script for "Halt core at power-on reset" is attached. But you have to do power off-on cycle in any case.

It is necessary to find the source of reset. You can check it in RGM_FES and RGM_DES registers. It is usually caused by watchdog.

Regards,

Lukas

[chfakhtchfakht]

lukaszadrapa For now i have tried  the cmm file (it tell me to power on/off) but after that i get the following

error: ERROR while releasing RESET: timeOut

Is there anything to do in this case or any other scripts that i can try

thanks

[petervlna]

Hi,

I would really appreciate if you do not multiply the threads.

Peter