Can not config CLKOUT pin on DEVKIT-MPC5744P

[everkimage]

I use example project Hello_World_PLL.

I Config PLL0 to 160MHz and use PLL0.PHI1 to support PLL1 to 200MHz.

Then make PLL1 support to SystemClock and CLKOUT pin output.

Finally i config the SIUL2.MSCR[PB6]=0x02000001,which means SSS=1(CLKOUT0),but SIUL2.MSCR[PB6] always get 0.

When i change to use PLL0 to support SystemClock,It's ok.

Is there something wrong?Please help.

Codes:
MC_CGM.AC3_SC.B.SELCTL = 1; //40 MHz XOSC selected as input of PLL0
PLLDIG.PLL0DV.B.RFDPHI1 = 8;
PLLDIG.PLL0DV.B.RFDPHI = 2;
PLLDIG.PLL0DV.B.PREDIV = 1;
PLLDIG.PLL0DV.B.MFD = 8;

MC_ME.DRUN_MC.R = 0x00130072;
MC_ME.MCTL.R = 0x30005AF0;
MC_ME.MCTL.R = 0x3000A50F;
while(MC_ME.GS.B.S_MTRANS == 1); /* Wait for mode transition complete */

MC_CGM.AC4_SC.B.SELCTL=0b11; //PLL0_PHI1 selected as input of PHI1
PLLDIG.PLL1DV.B.RFDPHI = 2;
PLLDIG.PLL1DV.B.MFD = 20;
PLLDIG.PLL1FD.B.FRCDIV = 0;

MC_ME.DRUN_MC.R = 0x001300F4;   //If i change this to 0x001300F2,it's ok.
MC_ME.MCTL.R = 0x30005AF0;
MC_ME.MCTL.R = 0x3000A50F;
while(MC_ME.GS.B.S_MTRANS == 1); /* Wait for mode transition complete */

/* Set Up clock selectors to allow clock out 0 to be viewed */
MC_CGM.AC6_SC.B.SELCTL = 4; /* Select PLL1 (PLL1-sysclk0) */
MC_CGM.AC6_DC0.B.DE = 1; /* Enable AC6 divider 0 (SYSCLK0)*/
MC_CGM.AC6_DC0.B.DIV = 9; /* Divide by 10 */

/* Configure Pin for Clock out 0 on PB6 */
SIUL2.MSCR[PB6].R = 0x02000001; /* PB6 = 22 SRC=2 (Full drive w/o slew) SSS=1 (CLKOUT_0) */

[PetrS]

Hi,

I can run the PLL1/system at 200MHz with below setting

// Enable XOSC, PLL0, PLL1 and enter RUN0 with PLL1 as sys clk (200 MHz)
void SysClk_Init(void)
    {
          MC_CGM.AC3_SC.B.SELCTL = 0x01;            //connect XOSC to the PLL0 input
          MC_CGM.AC4_SC.B.SELCTL = 0x03;            //connect PLL0-PHI1 to the PLL1 input

          // Set PLL0 to 160 MHz with 40MHz XOSC reference
          PLLDIG.PLL0DV.R = 0x40021008;         // PREDIV =  1, MFD = 8, RFDPHI = 2, RFDPHI1 = 8

          MC_ME.RUN0_MC.R = 0x00130070;            // RUN0 cfg: IRCON,OSC0ON,PLL0ON,syclk=IRC

          // Mode Transition to enter RUN0 mode:
          MC_ME.MCTL.R = 0x40005AF0;            // Enter RUN0 Mode & Key
          MC_ME.MCTL.R = 0x4000A50F;            // Enter RUN0 Mode & Inverted Key
          while (MC_ME.GS.B.S_MTRANS) {};            // Wait for mode transition to complete
          while(MC_ME.GS.B.S_CURRENT_MODE != 4) {};        // Verify RUN0 is the current mode

          // Set PLL1 to 200 MHz with 40MHz PLL0-PHI1 reference
          PLLDIG.PLL1DV.R = 0x00020014;         // MFD = 20, RFDPHI = 2

          MC_ME.RUN_PC[0].R = 0x000000FE;            // enable peripherals run in all modes
          MC_ME.RUN0_MC.R = 0x001300F4;            // RUN0 cfg: IRCON, OSC0ON, PLL1ON, syclk=PLL1

          MC_CGM.SC_DC0.R = 0x80030000;    // PBRIDGE0/PBRIDGE1_CLK at syst clk div by 4 ... (50 MHz)

          // Mode Transition to enter RUN0 mode:
          MC_ME.MCTL.R = 0x40005AF0;            // Enter RUN0 Mode & Key
          MC_ME.MCTL.R = 0x4000A50F;            // Enter RUN0 Mode & Inverted Key
          while (MC_ME.GS.B.S_MTRANS) {};            // Wait for mode transition to complete
          while(MC_ME.GS.B.S_CURRENT_MODE != 4) {};        // Verify RUN0 is the current mode
}

BR, Petr

[everkimage]

Thank you Petr.

According to your codes,i found that it's only need to add one code to make SIUL2.MSCR[PB6].R modifiable(I still use DRUN mode):

MC_CGM.SC_DC0.R = 0x80030000;    // PBRIDGE0/PBRIDGE1_CLK at syst clk div by 4 ... (50 MHz)

But i do not understand why?

But if i config MCU change to RUN0 from DRUN,there's no need to enable the SC_DC0 and SIUL2.MSCR[PB6].R is modifiable too.

why?

[everkimage]

I change the PLL1's frequency to 100MHz and successfully config the SIUL2.MSCR[PB6].R too.

Can not the PLL1's frequency be set to  200MHz?Or i set it wrong?If yes,how can i set it to 200MHz?