If I understand you well, you are looking for SPR number of cache control registers. You may find it in the core reference manual as on the screenshot below:
MSR does not have any number, it is special register and access goes over mtmsr anf mfmsr instructions.
If you meant your question otherwise, please clarify.
Real to effective address relation is not affected by cache. It is given by MMU setting.
Cache itself is not memory mapped.
But usually debuggers are capable to show cached content as shown below, for instance.
