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******************************************************************************** * Detailed Description: * This example shows how to reprogram the shadow flash. * * It is highly recommended to read application note "Preventing Device Lockout * via Censorship on MPC55xx and MPC563x Families" * http://www.freescale.com/files/32bit/doc/app_note/AN3787.pdf * * This examples erases the shadow flash, then it restores censorship information * and then NVUSRO nonvolatile register is reprogrammed to disable the watchdog. * The watchdog is disabled by clearing of bit WATCHDOG_EN in NVUSRO. It ensures * that watchdog is disabled automatically during startup of MCU. * Watchdog can be also disabled by software (shown in the code). * * It is important to execute the code from RAM memory because Read-While-Write * is not supported here. * * ------------------------------------------------------------------------------ * Test HW: XPC56xxMB2 + XPC560B 144LQFP, SPC5604B, silicon mask set 2M27V * Target : internal_FLASH, RAM * ********************************************************************************

This simple example shows the ADC setting for the scan mode and usage of Trimmer on TRK-MPC5604P board. Use Trimmer to dim the LED1. Regards, Petr ******************************************************************************** * Detailed Description: * * ADC testing and usage of Trimmer on TRK board * * ------------------------------------------------------------------------------ * Test HW: TRK-MPC5604P * Maskset: 0M36W * Target : internal_RAM * Terminal: no * Fsys: 64 MHz with 8 MHz XOSC reference * EVB connection: * * Use Trimmer to dim the LED1 * * NOTE! Be sure the ADC is powered, J21 5V jumper ON * ********************************************************************************

This config tool simplifies PLL setting calculation and clock configuration for MPC5777C device. Version 1.3 added option to select between 264/300 MHz MCU versions. Follow these steps Note: Macros have to be enabled! 1. Enter frequency of used XOSC and desired PLL0 and PLL1 output. - put values into cells B14, Q13 and Q20 of the "Clocks" sheet - check if it is Valid or Invalid - "PLLconfig" sheet shows possible PLLs configurations 2. Configure System and AUX clock selectors and its Dividers - check calculated frequency of System/Peripheral clocks - if Invalid change source clock and Divider value to keep Max freq 3. Copy generated code by pressing "Copy Code" button

******************************************************************************** * Detailed Description: * Example configure DRUN mode with PLL running at 160MHz. * It also contain basic PIT and INTC driver for interrupt demonstration. * On PIT timer timeout the PIT is triggering an interrupt which is served in PIT interrupt * service routine. * ------------------------------------------------------------------------------ * Test HW: X - PC5748G - MB (rev C) * MCU: PPC5748GMMN6A * Maskset: 1N81M * Fsys: 160 MHz * Debugger: Lauterbach Trace32 * * Target: Internal_FLASH * ********************************************************************************

The purpose of the example is to present advantage of streaming mode feature. Example initializes eQADC module, converts specified command queue and displays results into terminal window. Used analog inputs ANB_0 and ANB_1 requires external connection to converted voltage (potentiometer) to see some valid numbers. Following channels are being converted: CH0 = signal ANB_0 (connect pot USER_DEV_RV2(J4-7) --> ANB_0 (J19-3)) CH1= signal ANB_1 (connect pot USER_DEV_RV3(J4-8) --> ANB_1 (J19-4)) CH2 = may be left open (example configures the pin to be pulled-up) CH3 = may be left open (example configures the pin to be pulled-down) Result are being filled to 2 result queues to see loop switching in the terminal window when advance trigger occurs (results are displayed in two columns, 1st column is related to Rqueue0, 2nd to Rqueue1). Advance trigger occurs when EVB's USER switch 1 is being pressed (considering USER_DEV_1D(J4-2) --> TPU_A0 (J22-1)). Repeat trigger is initiated automatically by PIT3 timer in 1 sec intervals. eQADC command filled by eDMA, results drained by interrupt service routines. For detailed description SEE ATTACHED document.

******************************************************************************** * Detailed Description: * ECSM Error Generation Register EEGR is used to generate a non-correctable ECC * error in RAM. The bad data is accessed then, so the IVOR1 exception is * generated and handled. * This file shows also ECSM_combined_isr and how to correct the wrong data. * Use macro Induce_ECC_error_by_DMA_read to select whether ECC error will be * injected by DMA read or CPU read. * At the end of main file you can select particular ME/EE setup by * comment/uncomment of particular function calls. * * ------------------------------------------------------------------------------ * Test HW: XPC563MKIT * MCU: PPC5633MMLQ80 * Fsys: 80/60/40/12 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * * LINFlexD_1 configured as Master * - sends Header * - either transmits a data to LIN Slave or receives data from a LIN Slave * - no interrupt is used, just SW pooling * * LINFlexD_0 as Slave * - receives header from a LIN Master * - either receives data from a LIN Master or transmits a data to Master * - filter is enabled * - TX interrupt is used to prepare data to send and * - RX interrupt to read received data * * EVB connection: * * Switches on Motherboard: * P6.1 to P8.1 ... SW1 to PA0 * P6.2 to P8.2 ... SW2 to PA1 * P6.3 to P8.3 ... SW3 to PA2 * P6.4 to P8.4 ... SW4 to PA3 * * Unconnect LINFlexD_0 from UART transceiver * J14 SCI_RX open * J13 SCI_TX open * * As only single LIN transceiver is available LINFlex modules are connected * together before this transceiver in the way TX pins together and RX pins together. * TX pins must be configured as open drain and use a pullup resistor. * * P11.15 to P12.8 TX pins * P11.16 to P12.7 RX pins * * Connect LINFlexD_1 to LIN transceiver on Motherboard * J17 - LIN_TX ON * J16 - LIN_RX ON * J15 - LIN_EN ON * P3 1-2 ON ... VSUP to 12V ** * See LIN signal on P3.3 or J4.4. * * ------------------------------------------------------------------------------ * Test HW: MPC5744P * Maskset: 1N65H * Target : RAM, internal_FLASH * Fsys: 200 MHz PLL with 40 MHz crystal reference * Terminal: None ******************************************************************************** Revision History: 1.0 Feb-22-2016 PetrS Initial Version of LIN example *******************************************************************************/ Original Attachment has been moved to: Example-MPC5744P-LINFlex-LIN-Master-Slave-test-v1_0-GHS614.zip

WARNING 1: Use censorship feature very carefully, because an inappropriate usage can lead in making the device useless!!! Thoroughly read all instructions before use!!! WARNING 2: Version of ICDPPCNEXUS debugger that is included with CodeWarrior 2.10 is not capable to enable debug on certain devices including MPC5604B. Workaround is either using of Codewarrior 10.6 or using of PKGPPCNEXUS debugger - can be downloaded from P&E Microcomputer Systems WARNING 3: In case TRACE32 debugger is being used (Lauterbach), it is needed to have updated TRACE32 software. TRACE32 releases 02/2015 and 09/2016..02/2018 may not be able to access to censored device. LAUTERBACH DEVELOPMENT TOOLS The example consists of 2 parts and document describing how to access censored device via JTAG with using of PeMicro or Lauterbach debugger: 1) MPC5604B-Censor_device-CW210: ******************************************************************************** * Detailed Description: * The example code reprogram content of shadow flash to enable censorship. * After succesful operation LED1 is lighting. After power-on-reset the device * is censored with private 0xFEED_FACE_CAFE_BEEF. Subsequently the access can be * allowed by enabling debug of censored device as decipted in attached pdf * document. On this device password must be entered in reverse order i.e. * 0xCAFE_BEEF_FEED_FACE. Shadow flash re-programming code must be executed from * internal RAM. * ------------------------------------------------------------------------------ 2) MPC5604B-Uncensor_device-CW210: ******************************************************************************** * Detailed Description: * Supposing the device is censored by example MPC5604B-Censor_device-CW210 * Firstly it is needed to enabled debug of censored device as decipted in * attached pdf document. On this device password must be entered in reverse * order i.e.0xCAFE_BEEF_FEED_FACE. MPC5604B_run_from_ram.cmm script does it by * command SYStem.option.keycode 0xCAFEBEEFFEEDFACE. * Then run this code to uncensor the device. After succesful operation LED1 is * lighting. After power-on-reset the device is uncensored and subsequent access * will be without password. Shadow flash re-programming code must be executed * from internal RAM. * ------------------------------------------------------------------------------

******************************************************************************** * Detailed Description: * * Unlock, erase and program of flash mid block 0x00FB_8000 - 0x00FB_FFFF. * ------------------------------------------------------------------------------ * Test HW: X - PC5748G - MB (rev C) * MCU: PPC5748GMMN6A * Maskset: 1N81M * Fsys: 160 MHz * Debugger: Lauterbach Trace32 * * Target: Internal_FLASH * ********************************************************************************

MPC5xxx Documents Links to source codes for eTPU functions eQADC - avoiding unintended result swap External Bus Interface FAQs FlexCAN bit timing calculation Excel configurators MPC5xxx/S32Kxx: CAN / CAN FD bit timing calculation SW Drivers MPC5xxx I2C communication driver MPC55xx/56xx Documents e200 Core Training relevant to MPC55xx and MPC56xx device family Error Correcting Codes Implemented on MPC55xx and MPC56xx Excel configurators Excel MPC55xx/MPC56xx PLL Calculator MMU Assist Register CONFIGURATOR Debugger Scripts Example JTAG access – Addendum to application notes AN3283 and AN4365 MPC57xx Excel configurators Core MPU configurator MPC57xx - DCF records Debugger Scripts MPC57xx FCCU Utility scripts for Lauterbach debugger MPC5643L Documents MPC5643L PWM_ADC measurement concept GSH614 MPC5744P Documents MPC5744P_System_IO_Definition Using the Built-in Self-Test (BIST) on the MPC5744P Error Correcting Codes Implemented on MPC5744P MPC574xP - FCCU configuration guide Excel configurators Excel MPC5744P Clock Configurator MPC5744P DCF Configurator MPC5746R Documents MPC5746R STCU2 BIST configuration guide Excel configurators MPC5746R DCF Configurator MPC574xG/C Documents MPC5646C to MPC574xG Migration - Rev. 0, 09/2013 Draft only Excel configurators MPC5746C DCF Configurator MPC5748G DCF Configurator MPC5775K Excel configurators MPC5775K DCF Configurator MPC5777C Documents MPC5777C - Online BISTs Error Correction Codes Implemented on MPC5777C Excel configurators Excel MPC5777C clock configurator MPC5777C DCF Configurator MPC5777M Excel configurators MP5777M DCF Configurator S32R274 Excel configurators S32R274 DCF Configurator IDEs (CodeWarrior, S32 Design Studio) Documents How to program QSPI flash using CodeWarrior 10.x How to use CRCgen in CodeWarrior for MCU How to download separate elf/srec/hex file to microcontroller using S32 Design Studio How to use printf function in S32DS for Power Architecture using EWL library How to debug code using CodeWarrior 10.5 How to flash two .elf files using CodeWarrior 10.6 How to create FreeRTOS project in S32 Design Studio How to create new configuration in CodeWarrior for MCU For more HOWTOs related to S32 Design Studio, visit S32DS for Power - list of HOWTOs

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * Its intention is to offer advanced startup code additional to CW stationery. * ------------------------------------------------------------------------------ * Test HW: MPC5566EVB * MCU: PPC5566MVR132 * Fsys: 144/132/112/80/12 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: TPU_PORT_37 -> USER_LED_8 * TPU_PORT_38 -> USER_LED_7 (to see blinking LEDs) * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON) * by initialization of instruction cache and enabling of branch prediction. * Example suppose MCU is configured for LSM (Lock-step mode). * Its intention is to offer advanced startup code additional to CW stationery. * * ------------------------------------------------------------------------------ * Test HW: xPC564xLKIT, PPC5643L Cut3 silicon * Target : internal_FLASH, RAM * Fsys: 120 MHz PLL0 * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Terminal: 19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * IT INITIALIZES EBI FOR EXTERNAL SRAM CONNECTED TO XPC564AKIT324S AND TEST IT. * * ------------------------------------------------------------------------------ * Test HW: XPC564AKIT324S * MCU: SPC5644AMVZ1 0M14X QAK1235G * Fsys: 150/132/120/12 MHz * Debugger: Lauterbach Trace32 * Target: RAM, internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * Example show simple flash programming routine. During runtime it changes * content of field of constants 'test' (thus located in internal flash). * Also it shows how to relocate code into RAM a data into FLASH (used linker * command file is MPC5643L_my_sections.lcf and MPC5643L_DEBUG_my_sections.lcf). * * Note: For complex tasks use SSD driver (Freescale site for particular device, * Software&Tools/Run-Time Software/Middleware-Device Drivers * * ------------------------------------------------------------------------------ * Test HW: xPC564xLKIT, PPC5643L Cut3 silicon * Target : internal_FLASH, RAM * Fsys: 120 MHz PLL0 * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Terminal: 19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON) * by initialization of instruction/data cache and enabling of branch prediction. * Example suppose MCU is configured for DPM (Decoupled-parallel mode). * Its intention is to offer advanced startup code additional to CW stationery. * * ------------------------------------------------------------------------------ * Test HW: MPC5675KEVB * MCU: PPC5675KFMMSJ in Decoupled-parallel mode * Fsys: 180/150 MHz CORE_CLK * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * * CAN0 module is configured to transmit one message with ID 0x555 to CAN1 * module. CAN1 module is configured to use DMA to receive the message. * Once the DMA module reads the received frame, interrupt is triggered. * Follow application note AN4830 regarding the CAN settings. * http://www.freescale.com/files/microcontrollers/doc/app_note/AN4830.pdf * http://www.freescale.com/files/microcontrollers/doc/app_note/AN4830SW.zip * The example from AN4830 is modified to use DMA and RXFIFO on CAN1 module. * * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N81M * Target : SRAM * Fsys: 160 MHz PLL * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop (by second core), initializes and display notice via UART terminal and * then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * For XPC567XKIT516 it initializes EBI for mounted external SRAM device. * * ------------------------------------------------------------------------------ * Test HW: XPC567XKIT516 - MPC567xADAT516 Rev.D, MPC567XEVBFXMB Rev.C * MCU: PPC5676RDMVY1 3N23A * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys: 180MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: ETPUC0(J24-0) -> USER_LED_8 (J5-8) * ETPUC1(J24-1) -> USER_LED_7 (J5-7)(to see blinking LEDs) * ********************************************************************************

******************************************************************************** * Detailed Description: * * This example shows how to use SPI module in extended SPI mode * - DSPI3 is configured as a master * - SPI1 is configured as a slave * - Frame size is configured to 32bit * - Two writes are necessary to load one 32bit frame to TX FIFO * - For more details about the timing settings see application note AN4830 * ------------------------------------------------------------------------------ * Test HW: MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU: PPC5748GMMN6A 1N81M * Fsys: 160 MHz PLL * Debugger: Lauterbach Trace32 * Target: internal_FLASH ********************************************************************************

******************************************************************************** * Detailed Description: * This example demonstrates PMC SW triggered self-test configuration and execution * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N15P and 0N15P * Target : internal_FLASH * Fsys: 200 MHz PLL with 40 MHz crystal reference * ******************************************************************************** Revision History: 1.0 Apr-04-2016 b21190(Vlna Peter) Initial Version 1.1 Apr-20-2017 b21190(Vlna Peter) added software PMC self-test *******************************************************************************/