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******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, * * Initializes the MCU including the FlexCAN peripherals. * Configures the FlexCAN to transmit and receive a CAN message. * * Individual RX masking was added to the last version of this example. * Three messages with different ID's are sent via FlexCAN_0 MB0 MB1 and MB2. * These messages are received by FlexCAN_1 MB0, MB1 and MB2 according to masking * register settings. * * For MB0 data receive is used interrupt. * * * ------------------------------------------------------------------------------ * Test HW: S32R274RRUEVB, MPC57xx Motherboard * MCU: S32R274KAMMM 1N58R * Fsys: PLL0 240MHz * Z4 Core 120MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: internal_FLASH (debug mode, debug_ram and release mode) * EVB connection: * * It is necessary to remove both J35 jumpers. * * * Connect J35.2 to PA14 (CAN_1 TX) * Connect J35.4 to PA15 (CAN_1 RX) * * CAN0 is connected internally to J37 (this pin is placed on daughter card) * * Connect CAN P5.2 to J37.2 (CAN_1 and CAN_0 CANL) * Connect CAN P5.1 to J37.1 (CAN_1 and CAN_0 CANH) * * This connection has to be observed, otherwise correct communication between * CAN modules is not guaranteed. * * ********************************************************************************

******************************************************************************** * Detailed Description: * * Configure the device to wake up by STM_0 timer. * Configure the device to enter STANDBY mode from DRUN * Once the device is woken up by STM_0, the device is restared becase * we wrote address of entry point to register MC_ME.CADDR[1].R * ------------------------------------------------------------------------------ * Test HW: MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU: PPC5748GMMN6A 1N81M * Fsys: Default * Debugger: Lauterbach Trace32 * Target: internal_FLASH ********************************************************************************

******************************************************************************** * Detailed Description: * Example shows how to use original eTPU sets available over eTPU Function * Selector ( https://www.nxp.com/webapp/etpu/ ) and integrate them into * S32 Design Studio Integrated Development Platform. Example is based on * Software Development Kit (SDK) startup, in the main function adds necessary * configuration to get eTPU run. * eTPU application itself is simple PWM configured with eTPU Graphical * Configuration Tool. Target CPU is 'Generic CPU with eTPU2', eTPU clock 100MHz. * User can shows PWM waves over pins PH[10] and PH[11]. * * Tip: AN4687 may be used as reference with note the different compiler is used. * References: http://www.nxp.com/files/soft_dev_tools/doc/app_note/AN4687.pdf * https://www.nxp.com/webapp/sps/download/license.jsp?colCode=ETPUGCT * ------------------------------------------------------------------------------ * Test HW: MPC5746R-176DC Rev.A2 + MPC57xx MOTHER BOARD Rev.C * MCU: SPC5743RMLU5 QCO1640 1N83M FEAEQL * Target: Debug_FLASH * EVB connection: ETPU0_A (Port PH[10]) --> scope * ETPU1_A (Port PH[11]) --> scope * Compiler: S32DS.Power.2017.R1 * SDK release: S32_SDK_S32PA_EAR_1.8.0 * Configurator: eTPU Graphical Configuration Tool 1.4.0.4 * Debugger: Lauterbach Trace32 ******************************************************************************** Revision History: Ver Date Author Description of Changes 0.1 Apr-04-2019 David Tosenovjan Initial version *******************************************************************************/

******************************************************************************** * Detailed Description: * This example shows, how to use overlay feature - how to remap SRAM over Flash * and Flash over Flash. The remapping is visible only in mirrored flash address * space. Normal address space is not affected. To see effect of the remapping, * read the comments and watch following addresses in debugger before and after * executing Overlay() function: * * Flash over Flash test case: * 0x0104_0000 * 0x0108_0000 * 0x0904_0000 * 0x0908_0000 * * SRAM over Flash test case: * 0x4003_0000 * 0x090C_0000 * * ------------------------------------------------------------------------------ * Test HW: DEVKIT-MPC5748G * MCU: PPC5748GSMKU6 0N78S * Fsys: PLL0 160MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH (debug mode) * EVB connection: NA * ********************************************************************************

******************************************************************************** * Detailed Description: * This example demonstrate how to configure CGM (clock generation module) * and supply by clock all main peripherals. At maximum available frequency for system * which is 265MHz. * ------------------------------------------------------------------------------ * Test HW: MPC57xx Motherboard + MPC5775K_356DS minimodule, MPC5775K, * Maskset: 0N76P * Target : internal_FLASH * Fsys: 265 MHz PLL0 * ******************************************************************************** Revision History: 1.0 Apr-15-2015 b21190(Vlna Peter) Initial Version *******************************************************************************

******************************************************************************** * Detailed Description: * This example demonstrates basic interrupt functionality. * ------------------------------------------------------------------------------ * Test HW: MPC56xx Motherboard + XPC564xB/C 208LQFP * Maskset: 0N32E * Target : internal_FLASH * Fsys: 16MHz IRC as system clock ******************************************************************************** Revision History: 1.0 Mar-13-2017 b21190(Vlna Peter) Initial Version *******************************************************************************/

******************************************************************************** * Detailed Description: * Initializes eQADC module and cyclically converts chosen channel, displaying * it into terminal window. * User could connect EVB pot's wiper to pin header W (see below) to see valid * conversion result. * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: For ADC: J53-1 (EVB pot's wiper) --> PW7 - ANB16 * PW8 - ANB17 * PW9 - ANB18 * PW10 - ANB19 ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals. * * This example shows, how to use ADC with ETimer to dim LED diode. Voltage on * the output of the trimmer is converted to digital value which is used to * control duty cycle of the PWM generated by ETimer. * * ------------------------------------------------------------------------------ * Test HW: MPC5775K-356DS, MPC57xx Motherboard * MCU: PPC5775KMMY3A 0N76P * Terminal: * Fsys: PLL0 266MHz * Z4 Core 133MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: internal_FLASH (debug mode, release mode) * EVB connection: UserLED1 connected to P19.4, connected jumper j53 * * * ********************************************************************************

******************************************************************************** * Detailed Description: * Application initializes FCCU and Software watchdog. After SWT timeout expires, * microcontroller is reset. * * Macro LONG_RESET defines, which reset is performed. If LONG_RESET is 1, long * reset is performed, else short reset is performed. * * ------------------------------------------------------------------------------ * Test HW: S32R274RRUEVB, MPC57xx Motherboard * MCU: S32R274KAMMM 1N58R * Fsys: PLL0 240MHz * Z4 Core 120MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: internal_FLASH (debug mode, debug_ram and release mode) * EVB connection: default * * ********************************************************************************

******************************************************************************** * Detailed Description: * * PIT channel 0 is used to generate 1sec interrupt where PA0 pin is toggled. * * ------------------------------------------------------------------------------ * Test HW: MPC5777M, MPC57xx Motherboard + MPC5777M_512DS minimodule * Maskset: 0N78H * Target : RAM, internal_FLASH * Fsys: 600 MHz PLL1 with 40 MHz crystal reference * core2 at 200MHz generated from PPL1 * Terminal: None ********************************************************************************

WARNING 1: Use censorship feature very carefully, because an inappropriate usage can lead in making the device useless!!! Thoroughly read all instructions before use!!! WARNING 2: Version of ICDPPCNEXUS debugger that is included with CodeWarrior 2.10 is not capable to enable debug on certain devices including MPC5644A. Workaround is either using of Codewarrior 10.6 or using of PKGPPCNEXUS debugger - can be downloaded from P&E Microcomputer Systems WARNING 3: In case TRACE32 debugger is being used (Lauterbach), it is needed to have updated TRACE32 software. TRACE32 releases 02/2015 and 09/2016..02/2018 may not be able to access to censored device. LAUTERBACH DEVELOPMENT TOOLS The example consists of 2 parts and document describes how to access censored device via JTAG with using of PeMicro or Lauterbach debugger: 1) MPC5644A-Censor_device-CW210: ******************************************************************************** * Detailed Description: * The example code re-programs content of shadow flash to enable censorship. * Succesful operation is confirmed by notices in terminal window on eSCI_A * (19200-8-no parity-1 stop bit-no flow control). * After power-on-reset the device is censored with private password * 0xFEED_FACE_CAFE_BEEF. Subsequently the access can be allowed by enabling * debug of censored device as decipted in attached pdf document. Shadow flash * re-programming code must be executed from internal RAM. * ------------------------------------------------------------------------------ 2) MPC5644A-Uncensor_device-CW210: ******************************************************************************** * Detailed Description: * Supposing the device is censored by example MPC5644A-Censor_device-CW210 * Firstly it is needed to enabled debug of censored device as decipted in * attached pdf document. Programmed password is 0xFEED_FACE_CAFE_BEEF. * MPC5644A_run_from_ram.cmm script does it by command * SYStem.option.keycode 0xFEEDFACECAFEBEEF. * Then run this code to uncensor the device. Succesful operation is confirmed by * notices in terminal window on eSCI_A (19200-8-no parity-1 stop bit-no flow * control). After power-on-reset the device is uncensored and subsequent access * will be without password. Shadow flash re-programming code must be executed * from internal RAM. * ------------------------------------------------------------------------------

******************************************************************************** * Detailed Description: * The example uses serial flash memory S25FL129P (connected to DSPI_PCS1) * that is connected to DSPI_B module (PCS1). No Dual or Quad I/O has been used. * SW uses polling mechanism. * The example at first read device ID, performs bulk erase of S25FL129P and then * programs some sample data specified in main function. Check reading is then * performed. During that some notices are displayed on the terminal window. * ------------------------------------------------------------------------------ * Test HW: XPC567XKIT516 - MPC567xADAT516 Rev.D, MPC567XEVBFXMB Rev.C * MCU: PPC5676RDMVY1 3N23A * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys: 180MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: default ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes and display notice via UART terminal and then terminal ECHO. It * calculates temperature using TSENS0 and TSENS1 and prints it to the terminal. * * ------------------------------------------------------------------------------ * Test HW: xPC564xLKIT, PPC5643L Cut3 silicon * Target : internal_FLASH, RAM * Fsys: 120 MHz PLL0 * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Terminal: 19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes and display notice via UART terminal. It calculates temperature * using TSENS and printes it to the terminal window. * ------------------------------------------------------------------------------ * Test HW: MPC5675KEVB * MCU: PPC5675KFMMSJ in Lock-Step mode * Fsys: 180/150 MHz CORE_CLK * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed frequency (48MHz) * Setup SIU, and demonstrate frequency modulation. * ------------------------------------------------------------------------------ * Test HW: XPC560B 64LQFP, XPC56XX EVB MOTHEBOARD Rev.C * MCU: SPC5602D * Cut: 1M18Y * Fsys: 48 MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB clkout pin : Port J7 - pin 0 * ********************************************************************************

******************************************************************************** * Detailed Description: * This example initializes SMPU_0 and SMPU_1 to cover all memory resources for * all masters. * Simple test is performed in this example: after initialization, SMPU_1 * configuration is changed to disable write access to last 4kB of RAM for * Process ID 1. Write acess is allowed for Process ID 0. * If this area is written by CPU while the Process ID is 1, exception will * occur due to access violation. * ------------------------------------------------------------------------------ * Test HW: MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU: PPC5748GMMN6A 1N81M * Fsys: 160 MHz PLL * Debugger: Lauterbach Trace32 * Target: internal_FLASH * ********************************************************************************

******************************************************************************** * Detailed Description: * Example configure DRUN mode with PLL running at 160MHz. * It also contain basic PIT and INTC driver for interrupt demonstration. * On PIT timer timeout the PIT is triggering an interrupt which is served in PIT interrupt * service routine. * ------------------------------------------------------------------------------ * Test HW: X - PC5748G - MB (rev C) * MCU: PPC5748GMMN6A * Maskset: 1N81M * Fsys: 160 MHz * Debugger: Lauterbach Trace32 * * Target: Internal_FLASH * ********************************************************************************