******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, * * Initializes the MCU including the FlexCAN peripherals. * Configures the FlexCAN to transmit and receive a CAN message. * * Individual RX masking was added to the last version of this example. * Three messages with different ID's are sent via FlexCAN_0 MB0 MB1 and MB2. * These messages are received by FlexCAN_1 MB0, MB1 and MB2 according to masking * register settings. * * For MB0 data receive is used interrupt. * * * ------------------------------------------------------------------------------ * Test HW:         S32R274RRUEVB, MPC57xx Motherboard * MCU:             S32R274KAMMM 1N58R * Fsys:            PLL0 240MHz *                    Z4 Core 120MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, debug_ram and release mode) * EVB connection: * * It is necessary to remove both J35 jumpers. * * * Connect J35.2 to PA14 (CAN_1 TX) * Connect J35.4 to PA15 (CAN_1 RX) * * CAN0 is connected internally to J37 (this pin is placed on daughter card) * * Connect CAN P5.2 to J37.2 (CAN_1 and CAN_0 CANL) * Connect CAN P5.1 to J37.1 (CAN_1 and CAN_0 CANH) * * This connection has to be observed, otherwise correct communication between * CAN modules is not guaranteed. * * ********************************************************************************

******************************************************************************** * Detailed Description: * * Configures the MCANs to transmit and receive a CAN message. * * In this config, MCAN_0 transmits a message. MCAN_1 receives the message. * * MCAN_0 sends message each 1sec. This interval is generated by PIT. * Single TX buffer is used to send n bytes. The message ID is changed for each * transmission. Two standard and 2 extended IDs are sent. * * MCAN_1 is configured to receive a message, SW polling is used. * There are 2 standard and 2 extended ID filter tables defined. Classic filter * configuration is set, means filter ID & mask. * Messages with matched standard ID are received into RXFIFO_0, messages with matched * extended ID then stored in RXFIFO_1. *   * EVB connection: * * J37 and J38 to position 2-3 to connect MCAN1 TX/RX to transceiver * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *           use USB connector (J21) on minimodule * * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

******************************************************************************** * Detailed Description: * * Configures the MCANs to transmit and receive a CAN FD message with or without * bit rate switching for data phase. This is defined by BRS macro. * Baudrate during arbitration phase is set to 500kbps, during data phase 1Mpbs * because of PHY used on the EVB. * * In this config, MCAN_0 transmits a message. MCAN_1 receives the message. * * MCAN_0 sends message each 1sec. This interval is generated by PIT. * Single TX buffer is used to send n bytes. The message ID is changed for each * transmission. Two standard and 2 extended IDs are sent. * * MCAN_1 is configured to receive a message, ISR is used to read new message. * There are 2 standard and 2 extended ID filter tables defined. Classic filter * configuration is set, means filter ID & mask. * Messages with matched standard ID are received into RXFIFO_0, messages with matched * extended ID then stored in RXFIFO_1. *   * EVB connection: * * J37 and J38 to position 2-3 to connect MCAN1 TX/RX to transceiver * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *           use USB connector (J21) on minimodule * * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

******************************************************************************** * Detailed Description: * * ------------------------------------------------------------------------------ * Test HW:  TRK-MPC5634M rev.B, SPC5634M * Maskset:  1M35Y * Target :  RAM * Terminal: no * Fsys:     64 MHz PLL with 8 MHz crystal reference * * 1. you have to use an external power supply to the board (SBC power)   2. The SBC chip must be initialized (via SPI interface) to turn on the CAN transceiver.   3. For ease of use, install the VSUP shunt on (jumper J5). This it to put 9 V on the SBC's DBG pin - refer to the SBC Data Sheet for more details about the DBG pin of the SBC chip.   4. This code initializes the MCU, then sends commands to the SBC chip over the SPI bus to turn on the CAN transceiver, then the FlexCAN_A module transmits a message out of the board.   I/O configuration for the TRK-MPC5634M CAN example:   SBC_TXD  (MPC5634M CANATX PCR[83] ALT1 function) SBC_RXD  (MPC5634M CANARX PCR[84] input function)   SPI bus between the MCU and SBC:   SBC_!CS    (MPC5634M DSPI_B CS0  ALT1 function PCR[105]) SBC_CLK    (MPC5634M DSPI_B SCK  ALT1 function PCR[102]) SBC_MOSI   (MPC5634M DSPI_B SOUT ALT1 function PCR[104]) SBC_MISO   (MPC5634M DSPI_B SIN  input function PCR[103])  * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, initializes interrupts, blinking * one LED by core e200z4a, second by core e200z4b, third by core e200z2, * initializes and display notice via UART terminal and then terminal ECHO. * * ------------------------------------------------------------------------------ * Test HW:         MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU:             PPC5748GMMN6A 1N81M * Fsys:            160 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_2 * ********************************************************************************

WARNING 1: Use censorship feature very carefully, because an inappropriate usage can lead in making the device useless!!! Thoroughly read all instructions before use!!!   WARNING 2: Version of ICDPPCNEXUS debugger that is included with CodeWarrior 2.10 is not capable to enable debug on certain devices including MPC5644A. Workaround is either using of Codewarrior 10.6 or using of PKGPPCNEXUS debugger - can be downloaded from P&E Microcomputer Systems   WARNING 3: In case TRACE32 debugger is being used (Lauterbach), it is needed to have updated TRACE32 software. TRACE32 releases 02/2015 and 09/2016..02/2018 may not be able to access to censored device. LAUTERBACH DEVELOPMENT TOOLS   The example consists of 2 parts and document describes how to access censored device via JTAG with using of PeMicro or Lauterbach debugger:   1) MPC5644A-Censor_device-CW210: ******************************************************************************** * Detailed Description: * The example code re-programs content of shadow flash to enable censorship. * Succesful operation is confirmed by notices in terminal window on eSCI_A * (19200-8-no parity-1 stop bit-no flow control). * After power-on-reset the device is censored with private password * 0xFEED_FACE_CAFE_BEEF. Subsequently the access can be allowed by enabling * debug of censored device as decipted in attached pdf document. Shadow flash * re-programming code must be executed from internal RAM. * ------------------------------------------------------------------------------   2) MPC5644A-Uncensor_device-CW210: ******************************************************************************** * Detailed Description: * Supposing the device is censored by example MPC5644A-Censor_device-CW210 * Firstly it is needed to enabled debug of censored device as decipted in * attached pdf document. Programmed password is 0xFEED_FACE_CAFE_BEEF. * MPC5644A_run_from_ram.cmm script does it by command * SYStem.option.keycode 0xFEEDFACECAFEBEEF. * Then run this code to uncensor the device. Succesful operation is confirmed by * notices in terminal window on eSCI_A (19200-8-no parity-1 stop bit-no flow * control). After power-on-reset the device is uncensored and subsequent access * will be without password. Shadow flash re-programming code must be executed * from internal RAM. * ------------------------------------------------------------------------------

******************************************************************************** * Detailed Description: * This example shows how to configure Wake up unit and CAN sampler. * Once the device is woken up from STOP mode by falling edge on CAN0RX pin, * the CAN sampler starts to sample this pin in given period. * FlexCAN module is not initialized and used in this example because the CAN * sampler is independent of FlexCAN. * ------------------------------------------------------------------------------ * Test HW:  XPC56xxMB2 + XPC560B 176LQFP, PPC5607B * Target :  internal_FLASH, RAM * Fsys:     64 MHz PLL * ********************************************************************************

******************************************************************************** * Detailed Description: * * * This example shows synchronization between eTimer, CTU and ADC modules. * The eTimer0 module timer 2 is initialized to generate PWM signal, and rising edge * of this signal is used to generate trigger signal for CTU module. The CTU module * use one command list with 4 ADC_0 channels. Single conversion mode is used, * so ADC0 ch0, ch1, ch2 and ch3 are sampled. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * * EVB connection: * * P8.1  - A[0]  .. GPIO output, used to see CTU-ADC ISR period * P9.1     - B[7]  .. ADC0 AN[0] input * P9.2     - B[8]  .. ADC0 AN[1] input * P16.4 - I[3] .. CTU0 EXT TRG output * * see CTU0 EXT TRG output signal (toggle on each trigger) on P16.4 with respect of eTimer PWM signals. * ********************************************************************************

******************************************************************************** * Detailed Description: * This example initializes SMPU_0 and SMPU_1 to cover all memory resources for * all masters. * Simple test case is used in this example: after initialization, SMPU * configuration is changed to disable write access to last 4kB of RAM. * Once this area is written by CPU, exception will occur due to access * violation. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N81M * Target :  SRAM * Fsys:     160 MHz PLL * ********************************************************************************

This example follows application notes AN3283 and AN4365. It is intended for users who develop own JTAG programmer. It shows how to implement basic functions: - enter debug mode during reset - enable external debug mode - OnCE access to GPR, SPR and memory - Nexus access to memory The example is written in PRACTICE script language using Trace32 debugger from Lauterbach (www.lauterbach.com). Low level functions for JTAG are used, so users can see sequences of ‘0’s and ‘1’s which are sent to JTAG interface. Used commands are described in this document: www2.lauterbach.com/pdf/general_ref_j.pdf This example was tested on MPC5607B device and VLE instruction set was used for OnCE access.

WARNING 1: Use censorship feature very carefully, because an inappropriate usage can lead in making the device useless!!! Thoroughly read all instructions before use!!!   WARNING 2: Version of ICDPPCNEXUS debugger that is included with CodeWarrior 2.10 is not capable to enable debug on certain devices including MPC5604B. Workaround is either using of Codewarrior 10.6 or using of PKGPPCNEXUS debugger - can be downloaded from P&E Microcomputer Systems   WARNING 3: In case TRACE32 debugger is being used (Lauterbach), it is needed to have updated TRACE32 software. TRACE32 releases 02/2015 and 09/2016..02/2018 may not be able to access to censored device. LAUTERBACH DEVELOPMENT TOOLS   The example consists of 2 parts and document describing how to access censored device via JTAG with using of PeMicro or Lauterbach debugger:   1) MPC5604B-Censor_device-CW210: ******************************************************************************** * Detailed Description: * The example code reprogram content of shadow flash to enable censorship. * After succesful operation LED1 is lighting. After power-on-reset the device * is censored with private 0xFEED_FACE_CAFE_BEEF. Subsequently the access can be * allowed by enabling debug of censored device as decipted in attached pdf * document. On this device password must be entered in reverse order i.e. * 0xCAFE_BEEF_FEED_FACE. Shadow flash re-programming code must be executed from * internal RAM. * ------------------------------------------------------------------------------   2) MPC5604B-Uncensor_device-CW210: ******************************************************************************** * Detailed Description: * Supposing the device is censored by example MPC5604B-Censor_device-CW210 * Firstly it is needed to enabled debug of censored device as decipted in * attached pdf document. On this device password must be entered in reverse * order i.e.0xCAFE_BEEF_FEED_FACE. MPC5604B_run_from_ram.cmm script does it by * command SYStem.option.keycode 0xCAFEBEEFFEEDFACE. * Then run this code to uncensor the device. After succesful operation LED1 is * lighting. After power-on-reset the device is uncensored and subsequent access * will be without password. Shadow flash re-programming code must be executed * from internal RAM. * ------------------------------------------------------------------------------

******************************************************************************** * Detailed Description: * * Example gives possible implementation of input signal period/freq measurement. * eTimer channel capture 1 and 2 features are used. CAPT1/CAPT2 capture counter * value on rising/falling edge of input signal. The FIFO is set to 2 entries * and ICF2 is monitored. Free-running mode is used here. * * eTimer channel 0-1 are cascaded to achieve 1sec/1Hz measuring with 32bit counter. * * DMA is used to read CAPT1/2 registers and form 32bit values used in calculation. * * EVB connection: *   P8.2  - A[1]  .. eTimer0 channel1 input signal *   P8.1  - A[0]  .. GPIO output, used to show measurement period * *   Route LINFlexD_0 TXD/RXD (PB2/PB3) signals to the main board RS-232 transceiver *   Daughtercard: *   J17.11–12 ON  .. Connect LINFlexD_0 TXD (PB2) to main board. *   J17.8–9 ON .. Connect LINFlexD_0 RXD (PB3) to main board. * *   Motherboard *   J14 - SCI_RX ON *   J13 - SCI_TX ON *   J25 - SCI_PWR ON * * connect pulse signal to the P8.2. * See results on PC terminal (19200, 8N1, None). * Change freq/duty of input signal. * * ------------------------------------------------------------------------------ * Test HW:  MPC5744P * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: 19200, 8N1, None ********************************************************************************

******************************************************************************** * Detailed Description: * * This example shows how to use CRC module. * - CRC32 is used * - byte stream is written into input register * - one test case uses direct access to CRC registers * - second test case uses DMA to write the data stream * - the results can be compared using this online calculator: *   http://www.zorc.breitbandkatze.de/crc.html * - screenshots from online calculator are attached * ------------------------------------------------------------------------------ * Test HW:         MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU:             PPC5748GMMN6A 1N81M * Fsys:            160 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes eQADC module, performs calibration and converts channel 146 * (voltage level of VDD) to check core voltage level and displays it into * terminal window. No external connection required excluding terminal via eSCI. * * ------------------------------------------------------------------------------ * Test HW:        XPC564AKIT208S and XPC564AKIT324S * MCU:            SPC5644AMMG1,0M14X and SPC5644AMVZ1,0M14X * Fsys:           150/132/120/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * * * This example shows usage of FlexPWM and Sine Wave generator (SGEN) modules. * The setting is selected in the way to have a PWM output signal synhronized with * SWG output signal. This is necessary for resolver usage in motor control appls. * The CTU_0 is triggered from FlexPWM_0's. The PMWB output rising edge is used here. * The CTU generates the eTIMER1_TRG signal, that is a trigger signal for the * SGEN module. The delay between PWMB and SGEN trigger is changed so you can see * the generated sinusoidal signal change phase against the PWMB output. * * See attached Excel sheet for calculation of parammeters used here (AUX0_clk_DIV0, * AUX0_clk_DIV1, SGEN_IOFREQ, PWM_PRESCALER, PWM_MODULO). * * This example is set for 9.765625KHz SGEN/PWM frequency. * * Note  because the SGEN trigger input is an asynchronous signal, it must be held high * for at least 2 SGEN clock cycles in order to capture the input trigger. * As the CTU generates the trigger as a pulse of single CTU clock width, the CTU clock must be * half of the SGEN clock at least. * * Use the AUX0_clk_DIV0 to test this behaviour. * * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * * EVB connection: * * P11.8 - D[7] .. SGEN output *          connected to FEC PHY's MIIMODE input on motherboard, *          to see full amplitude remove J26    * * P8.12    - A[11] .. FlexPWM A[0] output * P8.11    - A[10] .. FlexPWM B[0] output * * ********************************************************************************

******************************************************************************** * Detailed Description: * * Application initializes SPI0 module as a master and SPI2 module as a slave. * Data are sent from master to slave and from slave to master. Simple * polling method is used to determine, when data were sent/received. * Received data are saved to global variables. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777M-512DS, MPC57xx Motherboard * MCU:             PPC5777MQMVA8 0N78H * Fsys:            PLL0 300MHz *                    PLL1 300MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, debug_ram mode, release mode) * EVB connection:  P18.12 to P14.13 (CS_0) *                    P11.4 to P8.13 (SCK) *                    P11.1 to P11.5 (SOUT - SIN) *                    P11.8 to P12.9 (SIN - SOUT) * * ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows, how to use interrupt hardware vector mode. In the example * PIT0 interrupt and external interrupt source 1 are implemented. PIT interrupt * toggle LED every second, external interrupt causes IVOR1 exception. * * This example also shows, how to use exceptions, while HW vector mode is used. * After SW1 button is pressed, uninitialized RAM is read and IVOR1 exception is * reached. In IVOR1, only endless loop is implemented and micro has to be reset * externally if you want to get out from this loop. * * * For correct HW vector mode setup, following files was added to the project: * *  - exceptions.s *  - handlers_vle.s *  - HW_vector.c * * * Following files was modified (all changes are marked by comment): * *  - mem.ld *  - sections.ld *  - Vector.c *  - MPC57xx__Interrupt_Init.c * * *  Following files was removed from project (files are still place in project, but *  not compiled and linked) * *  - intc_sw_handlers.S *  - intc_SW_mode_isr_vectors_MPC5744P.c * * * * Test HW:         X-MPC5744P-144DC, MPC57xx motherboard * MCU:             PPC5744PFMLQ8 0N15P * Fsys:            200 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  User LED 1 connected to A0 (P8.0), *                    User switch SW1 connected to A1 (P8.1) * * * ------------------------------------------------------------------------------ * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop (by second core), initializes and display notice via UART terminal and * then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * For XPC567XKIT516 it initializes EBI for mounted external SRAM device. * * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC567xADAT516 Rev.D, MPC567XEVBFXMB Rev.C * MCU:             PPC5676RDMVY1 3N23A * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:            180MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  ETPUC0(J24-0) -> USER_LED_8 (J5-8) *                  ETPUC1(J24-1) -> USER_LED_7 (J5-7)(to see blinking LEDs) * ********************************************************************************

This example enters the MCU into STANDBY0 low power mode and wakes up to backup SRAM. The WKPU6 (PE[0]pin) is used to wake up the MCU.   Regards, Petr   ******************************************************************************** * Detailed Description: * * On the EVB use KEY2 to enter Standby. * Use KEY1 to wake up from Standby to a code in backup SRAM. * * In RUN mode the LED1 blinks very fast, second core toggels LED3 * In STANDBY all LEDs are off. * The wakeup code blinks LED1 and LED2 slowly. * * The macro WKP_CORE is used to select which core is used after MCU wakes up. * When z4 core is selected, it is also necessary to set the MMU otherwise exception * is generated when uncovered memory area is accessed. * This is not needed for z0 core due to lack of the MMU.  * * * ------------------------------------------------------------------------------ * Test HW:  XPC56xxMB2 + XPC564xB/C, SPC5646C 0N32E silicon * Target :  internal_FLASH * Fsys:     120 MHz PLL0 ********************************************************************************

Demo application MPC5606S-DEMO + LM75B + HIH-5030 + PCA8565 + GUI Simple weather station demo using 2 external sensors and  external real time clock/calendar   For detailed description SEE ATTACHED document. ------------------------------------------------------------------------------ Test HW:            MPC5606S-DEMO-V2 + LM75BD + HIH-5030 + PCA8565 sensors MCU:             PPC5606SEF OMLU 0M25V DD68391 XOTAC1003 Fsys:            64MHz Debugger:        Lauterbach Trace32 Target:          internal_FLASH Terminal:        none EVB connection:  1) Temperature sensor LM75B:                        J51.40 - F[6] -> LM75B SDA                        J51.43 - F[7] -> LM75B SCL                        J52.1  - 3.3V -> LM75B Vcc                        J50.1  - GND  -> LM75B Gnd                   2) Humidity sensor HIH-5030:                        J52.1  - 3.3V -> HIH-5030 Ve+                        J50.1  - GND  -> HIH-5030 Ve-                        J50.1  - ANS0 -> HIH-5030 Out                   3) External Real Time Clock:                        J51.40 - F[6] -> PCA8565 SDA                        J51.43 - F[7] -> PCA8565 SCL                        J52.1  - 3.3V -> PCA8565 Vcc                        J50.1  - GND  -> PCA8565 Gnd                                        *******************************************************************************