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******************************************************************************** * Detailed Description: * This example implements ADC driver and demonstrated the usage of ADC in BCTU mode. * When PIT timer exceeds the trigger is sent to BCTU and BCTU triggers ADC_0 conversion. ******************************************************************************** * Test HW: MPC57xx * Maskset: 1N81M * Target : SRAM * Fsys: 160 MHz PLL * ******************************************************************************** Revision History: 1.0 Oct-29-2014 b21190(Vlna Peter) Initial Version 1.1 Nov-20-2014 b21190(Vlna Peter) Modified for Cut2.0 1.2 Nov-20-2014 b21190(Vlna Peter) Added SWT_0 dissabling in startup 1.3 Mar-10-2016 b21190(Vlna Peter) Fixed clock configuraion for PLL 1.4 Mar-10-2016 b21190(Vlna Peter) Added ADC driver 1.5 Mar-16-2016 b21190(Vlna Peter) Added BCTU and PIT drivers *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, initializes interrupts, blinking * one LED by core e200z4a, second by core e200z4b, third by core e200z2, * initializes and display notice via UART terminal and then terminal ECHO. * * ------------------------------------------------------------------------------ * Test HW: MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU: PPC5748GMMN6A 1N81M * Fsys: 160 MHz PLL * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on LINFlexD_2 * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL1 to maximum allowed freq. PLL1 is system frequency, * PLL0 in initialized to 50MHz * initializes peripherals clock (MOTC_CLK is set to 5MHz) * initializes ETimer to count mode providing delay * initializes interrupts, blinking one LED by ETimer interrupt, * * * * Test HW: X-MPC5744PE257DC, MPC57xx motherboard * MCU: PPC5744PFMMM8 1N65H * Fsys: 200 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: internal_FLASH (debug mode, release mode) * EVB connection: User LED 1 connected to A0 (P8.0), * * * ------------------------------------------------------------------------------

******************************************************************************** * Detailed Description: * * eMIOS0 ch0 is set to SAIC mode generating interrupt on falling edge. * The IGF ch16, connected to eMIOSch0, is set to filter low pulses <1.5us * Intergation filter type is used for falling edge with given threshold. * eMIOS interrupt is called if input signal low pulse is longer than 1.5us. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * use USB connector (J21) on minimodule * * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * * eMIOS ch0 (PortG P14-16)--> connect external pulse signal * ********************************************************************************

******************************************************************************** * Detailed Description: * This example demostrates how to configure CGM )clock generation module) * and supply by clock all main peripherals. * * ------------------------------------------------------------------------------ * Test HW: Test HW: MPC57xx Motherboard + MPC5777M_512DS minimodule, MPC5777M, * Maskset: 0N75H * Target : internal_FLASH * Fsys: 200 MHz PLL * ******************************************************************************** Revision History: 1.0 Nov-04-2014 b21190(Vlna Peter) Initial Version 1.1 Feb-04-2016 b21190(Vlna Peter) Fixed Clock configuration *******************************************************************************

******************************************************************************** * Detailed Description: * * Application initializes SPI0 module as a master and SPI2 module as a slave. * Data are sent from master to slave and from slave to master. Simple * polling method is used to determine, when data were sent/received. * Received data are saved to global variables. * * ------------------------------------------------------------------------------ * Test HW: MPC5777M-512DS, MPC57xx Motherboard * MCU: PPC5777MQMVA8 0N78H * Fsys: PLL0 300MHz * PLL1 300MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: internal_FLASH (debug mode, debug_ram mode, release mode) * EVB connection: P18.12 to P14.13 (CS_0) * P11.4 to P8.13 (SCK) * P11.1 to P11.5 (SOUT - SIN) * P11.8 to P12.9 (SIN - SOUT) * * ********************************************************************************

******************************************************************************** * Detailed Description: * Used flash driver: MPC5700 C55FG Flash Standard Software Driver (REV 1.1.0) * http://www.nxp.com/files/product/software/C55_JDP_SSD.exe * * This example checks four large 256KB flash blocks at address 0x0100_0000 - * 0x010F_FFFF. * Some random data are placed to this section (constant "flash_data[]"), so the * s-record is not empty. * It is necessary to use off-line MISR_C55.exe tool which calculates MISR * values for selected flash blocks. See the "MISR gen" folder included in this * project. File "core0.run" is s-record file which is used for calculation. It * contains the data (constant "flash_data[]") placed to the selected blocks. * "misr.bat" file shows how to call the calculator. * "output.txt" contains the result of this operation - the MISR values. * Once this is done, initialize the SSD drivers, unlock blocks which are going * to be checked and run the FlashArrayIntegrityCheck function. * Notice that the code must be executed from RAM. We cannot access the flash * during this operation. If the operation is successful, FlashCheckStatus will * return opResult C55_OK if the MISR values are equal. It will return * C55_ERROR_MISMATCH if the MISR values are not equal, i.e. the flash is * corrupted and the content does not correspond to s-record file. * ------------------------------------------------------------------------------ * Test HW: X-MPC5744PE257DC, MPC57xx motherboard * MCU: PPC5744PFMMM8 1N65H * Fsys: 200 MHz PLL * Debugger: Lauterbach Trace32 * Target: internal_FLASH * ********************************************************************************

The example does exactly the same operation like this example: https://community.freescale.com/docs/DOC-105380 ...but SSD flash driver is used now. ******************************************************************************** * Detailed Description: * * Unlock, erase and program of flash mid block 0x00FB_8000 - 0x00FB_FFFF. * Used SSD flash drivers: * http://www.freescale.com/files/product/software/C55_JDP_SSD.exe * Version of the driver is v1.0.0 * ------------------------------------------------------------------------------ * Test HW: X - PC5748G - MB (rev C) * MCU: PPC5748GMMN6A * Maskset: 1N81M * Fsys: 160 MHz * Debugger: Lauterbach Trace32 * * Target: Internal_FLASH * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, setup access right for Masters and Peripherals * on AIPS_0 * * DMA transfers block of data from variable TransmitBuffer to the variable * ReceiveBuffer. Both variables are placed in SRAM. * * ICache and DCache are both disabled in startup file using CACHE_ENABLE macro. * You can change the value of the macro at the following path: * project Properties/C/C++ General/Paths and Symbols/Symbols * If you change the value to 1, ICahce and DCache will be enabled in startup. * * * ------------------------------------------------------------------------------ * Test HW: MPC5775K-356DS, MPC57xx Motherboard * MCU: PPC5775KMMY3A 0N38M * Fsys: PLL0 266MHz * Z4 Core 133MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: internal_FLASH (debug mode, release mode) * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, third LED by second core, initializes and display notice via UART * terminal and then terminal ECHO. * * ------------------------------------------------------------------------------ * Test HW: XPC56xxMB2 + XPC564xB/C, PPC5646C 0M87Y silicon * Target : internal_FLASH, RAM * Fsys: 120 MHz PLL0 * Debugger: Lauterbach Trace32. script for internal_FALSH run_from_flash.cmm * script for RAM: run_from_ram_vle.cmm * ********************************************************************************

******************************************************************************** * Detailed Description: * Sensor board OM11057A which includes two PCF8885 circuits is connected * to MPC5748G via I2C. MPC5748G continuously reads the state of touch sensors * and the state is shown on LED diodes which are driven by I2C circuit PCA9535. * * Used I2C driver: https://community.freescale.com/docs/DOC-330972 * * Touch sensor board (page 9 and 10): * http://www.nxp.com/documents/user_manual/UM10505.pdf * * ------------------------------------------------------------------------------ * * Connection: * * Connect I2C bus (I2C_2 on MPC5748G) to sensor board: * I2C_SCL: P24-33 (pin PE9) on MPC574XG-MB to K3-1 on OM11057A * I2C_SDA: P24-35 (pin PE8) on MPC574XG-MB to K3-13 on OM11057A * Note: use two pull-up resistors on I2C signals (pulled to 3.3V). * The value should be 3k3 - 10k * * Connect power supply from MPC574XG-MB to OM11057A: * GND: P24-2 on MPC574XG-MB to K3-7 on OM11057A * 3.3V: P24-1 on MPC574XG-MB to K3-9 on OM11057A * * Connect SLEEP pins of both PCF8885 to GND (this will ensure that sleep mode * is not entered): * SLEEP1: K3-11 to K2-3 (both on OM11057A) * SLEEP2: K1-6 to K1-8 (both on OM11057A) * * ------------------------------------------------------------------------------ * Sensor board: OM11057A * http://www.nxp.com/documents/user_manual/UM10505.pdf * Test HW: MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU: PPC5748GMMN6A 1N81M * Fsys: 160 MHz PLL * Debugger: Lauterbach Trace32 * Target: internal_FLASH * ********************************************************************************

/* * Queue.h * * Created on: May 28, 2015 * Author: ShuLizhong */ #ifndef QUEUE_H_ #define QUEUE_H_ #ifdef _cplusplus extern "C" { #endif /*If you want to change the queue type(QUEUE_TYPE) and queue max size(QUEUE_MAX_SIZE), you should define it at front of include queue.h file. eg: ******in xxx.h file***** code**** #define QUEUE_TYPE Other type(unsigned int) #define QUEUE_MAX_SIZE Other size(100) #include "qeue.h" code**** */ #ifndef QUEUE_TYPE #define QUEUE_TYPE unsigned char #endif #ifndef QUEUE_MAX_SIZE #define QUEUE_MAX_SIZE 100 #endif #define bool unsigned int typedef enum { OK, FULL, EMPTY }QUEUE_STATUS; typedef struct { unsigned int tail; unsigned int head; unsigned int size; unsigned int length; QUEUE_TYPE data[QUEUE_MAX_SIZE]; }Queue_tag,*pQueue_tag; __inline void InitQueue(pQueue_tag q) { q->tail = q->head = q->size = 0; q->length = QUEUE_MAX_SIZE; } __inline QUEUE_STATUS EnQueue(pQueue_tag q,QUEUE_TYPE data) { if(q->size++ == QUEUE_MAX_SIZE) return FULL; q->data[q->tail] = data; q->tail = (q->tail+1) % QUEUE_MAX_SIZE; return OK; } __inline QUEUE_STATUS DeQueue(pQueue_tag q, QUEUE_TYPE *data) { if(q->size-- == 0) return EMPTY; *data = q->data[q->head]; q->head = (q->head+1) % QUEUE_MAX_SIZE; return OK; } __inline bool IsQueueEmpty(pQueue_tag q) { return q->size == 0; } __inline bool IsQueueFull(pQueue_tag q) { return q->size == QUEUE_MAX_SIZE; } __inline unsigned int GetQueueSize(pQueue_tag q) { return q->size; } __inline unsigned int GetQueueLength(pQueue_tag q) { return q->length; } /*__inline unsigned int DeMoreBytesFromQueue(pQueue_tag q,QUEUE_TYPE *data,unsigned int len) { unsigned int i = 0; len++; return 0; }*/ #ifdef _cplusplus } #endif #endif /* QUEUE_H_ */

******************************************************************************** * Detailed Description: * * LINFlexD_1 configured as Master * - sends Header * - either transmits a data to LIN Slave or receives data from a LIN Slave * - no interrupt is used, just SW pooling * * LINFlexD_0 as Slave * - receives header from a LIN Master * - either receives data from a LIN Master or transmits a data to Master * - filter is enabled * - TX interrupt is used to prepare data to send and * - RX interrupt to read received data * * EVB connection: * * LIN1 circuitry * connect 12V to LIN1-VSUP, so connect J23.1 to P11.3 * J13, J12 jumpers placed * * LIN0 circuitry * remove J11 * * connect LIN1 to LIN0, so connect P11 to P9 * if do not have desired cable, connect P11.3-P9.3 and P11.4-P9.4 * * See LIN signal on P11.4 or P9.4. * * ------------------------------------------------------------------------------ * Test HW: X-MPC574xG-324DS + X-MPC574XG-MB * Maskset: 1N81M * Target : FLASH * Fsys: 160 MHz PLL * ********************************************************************************

This session will explain how Freescale can enable customers to develop 76-81 GHz short and long range radar applications using the MPC577xK MCU, it will explain the concepts of the radar algorithms, including practical aspects such as SDADC or MIPI CSI sampling, Chirp Generation, Data Compression, R,V FFT, Detection and Tracking algorithms, and the benefits of the new Freescale IP that can allow them to improve their system resolution and accuracy. In this session customers will take away a detailed understanding of how to develop fast modulation radar systems using the MPC577xK MCU including the BOM cost advantages it also brings.

******************************************************************************** * Detailed Description: * * Application performs basic initialization, setup PLLs. * DSPI_A is configured as master using DMA to send/receive 8 words. * * Two DMA descriptors are initialized: * - TCD[32] master transmit * - TCD[33] master receive * * * EVB connection: * * Do external loopback to connect SOUT to SIN * * PM6 ... SCKA * PM7 ... SINA * PM8 ... SOUTA * PM13... PCSA0 ** * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 3N45H * Fsys: PLL1 = core_clk = 260MHz, PLL0 = 200MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * *********************************************************************************

******************************************************************************** * Detailed Description: * * Configures the MCANs to transmit and receive a CAN FD message with or without * bit rate switching for data phase. This is defined by BRS macro. * Baudrate during arbitration phase is set to 500kbps, during data phase 1Mpbs * because of PHY used on the EVB. * * In this config, MCAN_0 transmits a message. MCAN_1 receives the message. * * MCAN_0 sends message each 1sec. This interval is generated by PIT. * Single TX buffer is used to send n bytes. The message ID is changed for each * transmission. Two standard and 2 extended IDs are sent. * * MCAN_1 is configured to receive a message, ISR is used to read new message. * There are 2 standard and 2 extended ID filter tables defined. Classic filter * configuration is set, means filter ID & mask. * Messages with matched standard ID are received into RXFIFO_0, messages with matched * extended ID then stored in RXFIFO_1. * * EVB connection: * * J37 and J38 to position 2-3 to connect MCAN1 TX/RX to transceiver * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.D + MPC57xx MOTHER BOARD Rev.C * MCU: SPC5777CCMM03 3N45H * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * use USB connector (J21) on minimodule * * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

******************************************************************************** * Detailed Description: * * Configure the device to wake up by STM_0 timer. * Configure the device to enter STANDBY mode from DRUN * Once the device is woken up by STM_0, the device is restared becase * we wrote address of entry point to register MC_ME.CADDR[1].R * ------------------------------------------------------------------------------ * Test HW: MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU: PPC5748GMMN6A 1N81M * Fsys: Default * Debugger: Lauterbach Trace32 * Target: internal_FLASH ********************************************************************************