LPSPI TX FIFO not draining on RT1050?

[jackking]

Is the TX FIFO for LPSPI supposed to update automatically after a writedata?

I am checking the FIFO count and never see it drain when it fills up, so I must be missing something.

Here is my code for writing SPI data and checking the FIFO (based on LPSPI driver example):

LPSPI_WriteData(EXAMPLE_LPSPI_MASTER_BASEADDR, data);

while(LPSPI_GetTxFifoCount(EXAMPLE_LPSPI_MASTER_BASEADDR) > (g_masterFifoSize - 2))
{
//wait until some space becomes available
}‍‍‍‍‍‍

[jackking]

OK, answering my own question in case anyone hits a similar issue.

Since my SPI device is only receiving data and never sending it, I needed to mask the rt1050 RX FIFO, by setting RXMSK in the TCR:

   EXAMPLE_LPSPI_MASTER_BASEADDR->TCR =
        (EXAMPLE_LPSPI_MASTER_BASEADDR->TCR &
         ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_PCS_MASK)) |
           LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_CONT(1) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(0) | LPSPI_TCR_TXMSK(0) | LPSPI_TCR_PCS(whichPcs);‍‍‍‍‍‍‍‍

It looks like the RX FIFO was filling up and I wasn't reading it to empty it, and this blocked the TX FIFO.

thanks