DTC or OC SRAM?

[Daan]

Since my DTC SRAM got filled over 100%, I moved some of my code from DTC SRAM to OC SRAM, I achieved so by configuring bss to OC in file linkscripts/bss.ldt:

<#if memory.name=="SRAM_OC">

/* Custom bss.ldt */
*(.bss*)
/* End of custom bss.ldt */

</#if>

However, the application now seems to start, but gets stuck in a FreeRTOS loop, before the modification, all ran just fine; what am I missing? Why is there such a difference between DTC and OC SRAM?

[Daan]

I found another topic about this issue, the poster had the same problem  (Linkscripts and howto put all datafrom a specific object file ) His solution is to configure critical memory to DTC, but how will I know whether a file contains critical memory? I'm using FreeRTOS together with lwip, I can't decide which file is critical or not...

[jingpan]

Hi,

The most critical data is the buffer that accessed by both CPU and DMA, for example the LWIP descriptor and input/output buffer. Because OC RAM and external RAM default use cache to accelerate access. But CPU always read cache if data is buffered in cache. He won't know it is covered by ENET DMA. This will cause may kinds of error.

For example, you can modify the code in this way

err_t ethernetif0_init(struct netif *netif)
{
    static struct ethernetif ethernetif_0;
    AT_NONCACHEABLE_SECTION_ALIGN(static enet_rx_bd_struct_t rxBuffDescrip_0[ENET_RXBD_NUM], FSL_ENET_BUFF_ALIGNMENT);
    AT_NONCACHEABLE_SECTION_ALIGN(static enet_tx_bd_struct_t txBuffDescrip_0[ENET_TXBD_NUM], FSL_ENET_BUFF_ALIGNMENT);
//    SDK_ALIGN(static rx_buffer_t rxDataBuff_0[ENET_RXBD_NUM], FSL_ENET_BUFF_ALIGNMENT);
//    SDK_ALIGN(static tx_buffer_t txDataBuff_0[ENET_TXBD_NUM], FSL_ENET_BUFF_ALIGNMENT);
    AT_NONCACHEABLE_SECTION_ALIGN(static rx_buffer_t rxDataBuff_0[ENET_RXBD_NUM], FSL_ENET_BUFF_ALIGNMENT);
    AT_NONCACHEABLE_SECTION_ALIGN(static tx_buffer_t txDataBuff_0[ENET_TXBD_NUM], FSL_ENET_BUFF_ALIGNMENT);

    ethernetif_0.RxBuffDescrip = &(rxBuffDescrip_0[0]);
    ethernetif_0.TxBuffDescrip = &(txBuffDescrip_0[0]);
    ethernetif_0.RxDataBuff = &(rxDataBuff_0[0]);
    ethernetif_0.TxDataBuff = &(txDataBuff_0[0]);

    return ethernetif_init(netif, &ethernetif_0, 0U, (ethernetif_config_t *)netif->state);
}

Regards,

Jing

[Daan]

Thanks for your reply. I see what you mean, but I have many many files, with lots of buffers, lists and queues, how can I tell which parts are critical, or like you say, how do I know if they are accessed by the CPU and DMA?

[jingpan]

Hi,

Another way is to enlarge DTC RAM size. Please refer to AN12077.

[Daan]

Thanks again for your answer. Unfortunately, the DTC RAM will not suffice, even if I increase it. My project needs more memory than available in DTC, so I need to use the OC RAM. So I still would like to know how I can tell what memory needs to be non-cachable?

[jingpan]

Hi @Daan ,

You have check them one by one.