how to config DDR init in BL2

[__OTL__]

Hi 

We are bringing up our custom ls1046a board using 4 * 2GB DDR4 chips.

(We refered to LS1046AFRWY, doubled the capacity and removed ECC)

First I generated BL2 binary with

make PLAT=ls1046afwry bl2 BOOT_MODE=qspi pbl RCW=/atf/PBL_binary.bin

And we got this:

NOTICE: Fixed DDR on board
ERROR: Found training error(s): 0x2100
ERROR: Error: Waiting for D_INIT timeout.
ERROR: Writing DDR register(s) failed
ERROR: Programing DDRC error
ERROR: DDR init failed.
NOTICE: Incorrect DRAM0 size is defined in platfor_def.h
ERROR: mmap_add_region_check() failed. error -22
ERROR: mmap_add_region_check() failed. error -22
NOTICE: BL2: v1.5(release):LSDK-20.12-dirty
NOTICE: BL2: Built : 18:55:21, Oct 25 2022
ERROR: BL2: Failed to load image (-2)
Authentication failure

I think we have to change the config in atf\plat\nxp\soc-ls1046\ls1046ardb\ddr_init.c but I have no idea what they mean.

Is there any tool to generate the config easily or any document descibed the parameters' meanings?

[yipingwang]

It is necessary to purchase CodeWarrior TAP and CodeWarrior license to do DDR validation with DDRv tool.

In QCVS DDR project, please refer to file "ddr_init1.c" in folder Generated_Code to modify atf/plat/nxp/soc-ls1046a/ls1046afrwy/ddr_init.c.

You need to modify the following section if you use read from SPD method.

static const struct rc_timing rcz[] = {
{1600, 8, 7},
{2100, 8, 7},
{}
};

static const struct board_timing ram[] = {
{0x1f, rcz, 0x01010101, 0x01010101},
};

[__OTL__]

Thanks.

In QCVS DDR project, please refer to file "ddr_init1.c" in folder Generated_Code to modify atf/plat/nxp/soc-ls1046a/ls1046afrwy/ddr_init.c.

Here are all files in the Generated_Code folder.
How to generate ddr_init1.c ?

We are using discrete DDR so there is no SPD to read.

[yipingwang]

You could modify ddr_raw_timing according to your DDR data sheet, then build atf image and deploy it to our custom board. Then use QCVS DDR tool to connect to your custom board to read from target board to create a QCVS DDR project.

You also could create a default QCVS DDR project for LS1046A, then modify Properties panel according to your DDR data sheet.

Then use QCVS DDRv tool to connect to your target board to do validation and optimization to get the optimized DDR controller configuration parameters.

1. You could define CONFIG_STATIC_DDR in plat/nxp/soc-ls1046a/ls1046afrwy/platform_def.h, and use static DDR configuration parameter.

 2. You also could use DDR raw timing and modify rc timing and board timing in plat/nxp/soc-ls1046a/ls1046afrwy/ddr_init.c calculated by DDRv tool.

Which version CodeWarrior are you using? You could refer to ddrTfa_1.c.

[__OTL__]

Yes, I defined CONFIG_STATIC_DDR in platform_def.h 

You mentioned I can use  ddr_init1.c generated by QCVS DDR project, but I can't find it in the Generated_Codes folder. What should I do?

The soft version is

CodeWarrior Development Studio for QorIQ LS series - ARM V8 ISA

Copyright 2016-2020 NXP. (c) Freescale Semiconductor, Inc. 2014-2016. All rights reserved.
Learn more about CodeWarrior at
http://www.nxp.com/codewarrior

Version: 11.5.0
Build Id: 200629GA 

[yipingwang · Accepted solution]

Please use parameters defined in file ddrTfa_1.c.

[__OTL__]

Hi Yiping

Thanks for the answer.

I tried the QCVS DDR tool and generated the code, but still I don't know how to implement the generated code to BL2?

About validation:

We don't have the JTAG TAP and the license so I can't do the validation. My goal is just to boot u-boot and linux, so I think maybe for now a not so bad DDR config is good enoungh?

If everything goes well we will do the DDR optimization in the future.

I am using the evaluation version QCVS tool, if I buy the JTAG TAP can we do the validation using evaluation version soft? or we need to buy the license?

[yipingwang]

You could refer to section "DDR Board Level Applications" in LSDK 21.08 document https://docs.nxp.com/bundle/GUID-487B2E69-BB19-42CB-AC38-7EF18C0FE3AE/page/GUID-903DCB6A-FA4B-4A1C-B...

We recommend customers use QCVS DDRv tool to calculate, validate and optimize DDR configuration parameters. Please refer to the attached user manual.

You could create a QCVS DDR project with reading from SPD method, then connect this project to your target board to do optimization and validation to get the optimized parameters, use these parameters to modify ATF source code.