LS1043A custom board 5 seconds delay to boot after porting LSDK21.08

[wangyf]

Hi, 

We are having a custom board based on ls1043a , We used uboot 2018.09 before, everything works well, but when I porting to uboot 2021.04 based on LSDK21.08 ,  every time when I power on or reboot the board, there will be 5 seconds delay to boot. After the board booting up , the board works well.

I can ensure that ddr parameters of the board works well, can the team help me to solve the problem ? 

thanks very mach.

My all configration on uboot , please refer to attachment: u-boot.txt (it is u-boot.cfg file)

Here is the boot log:

=> reset   （or power on）
resetting ...

（About 5 seconds delay here, and noting prints here, after 5s delay, the uboot begin to work）

U-Boot 2021.04-g2022-03-17-8e84f87 (Mar 18 2022 - 16:45:11 +0800)

SoC: LS1043AE Rev1.1 (0x87920011)
Clock Configuration:
CPU0(A53):1600 MHz CPU1(A53):1600 MHz CPU2(A53):1600 MHz
CPU3(A53):1600 MHz
Bus: 400 MHz DDR: 1600 MT/s FMAN: 500 MHz
Reset Configuration Word (RCW):
00000000: 08100010 0a000000 00000000 00000000
00000010: 45580002 00004012 40025000 c1002000
00000020: 00000000 00000000 00000000 00038802
00000030: 20024104 00001102 00000096 00000001
Model: Yytek LS1043A Board
Board: Yytek LS1043A, boot from QSPI
I2C: ready
DRAM: Initialzing DDR using fixed setting
Configuring DDR for 1600 MT/s data rate
7.9 GiB (DDR4, 32-bit, CL=12, ECC off)
Using SERDES1 Protocol: 17752 (0x4558)
SEC Firmware: Bad firmware image (not a FIT image)
WARN: pls set popts->cpo_sample = 0x44 in <board>/ddr.c to optimize cpo
CPU: 4 cores online
MMC: FSL_SDHC: 0
Loading Environment from EEPROM... OK
Loading NVM information... : OK
In: serial
Out: serial
Err: serial
SEC0: RNG instantiated
Net: SF: Detected n25q256ax1 with page size 256 Bytes, erase size 4 KiB, total 32 MiB
Fman1: Uploading microcode version 106.4.18
yt8521 phy init
Could not get PHY for FSL_MDIO0: addr 2
Failed to connect
PCIe1: pcie@3400000 Root Complex: no link
PCIe2: pcie@3500000 Root Complex: no link
PCIe3: pcie@3600000 disabled
FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4
Warning: FM1@DTSEC4 (eth3) using random MAC address - 9a:a1:f4:cb:fe:41
, FM1@DTSEC5, FM1@DTSEC6

[wangyf · Accepted solution]

Hello, 

Thanks for your replay, QSPI Clock setting is no problem, we do not enable TFA_BOOT on my custom board, so DDR and cache is not init before relocation,  follwing patch solve the problem: we don't scan devicetree's node not needed before relocation

diff --git a/drivers/core/root.c b/drivers/core/root.c
index 9bc682c..8469a87 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -232,6 +232,8 @@ static int dm_scan_fdt_node(struct udevice *parent, ofnode parent_node,
node = ofnode_next_subnode(node)) {
const char *node_name = ofnode_get_name(node);

+ if (pre_reloc_only && !ofnode_pre_reloc(node))
+ continue;
if (!ofnode_is_enabled(node)) {
pr_debug(" - ignoring disabled device\n");
continue;

[wangyf]

Hello,  

Thanks for your replay, RCW about QSPI's clock setting is no problem, my custom board is not enable TFA_BOOT,  DDR and cache is not init before relocation, following patch solved the problem: don't scan devicetree's node not needed before relocation

diff --git a/drivers/core/root.c b/drivers/core/root.c
index 9bc682c..8469a87 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -232,6 +232,8 @@ static int dm_scan_fdt_node(struct udevice *parent, ofnode parent_node,
node = ofnode_next_subnode(node)) {
const char *node_name = ofnode_get_name(node);

+ if (pre_reloc_only && !ofnode_pre_reloc(node))
+ continue;
if (!ofnode_is_enabled(node)) {
pr_debug(" - ignoring disabled device\n");
continue;

if node is not needed in SPL/TL, we do not scan it to reduce boot up time

[teddy_gom_e]

Hello,

Does your custom board boot on QSPI. In this case maybe this is the QSPI clock speed divisor that is not adapted and it slowly copy application from QSPI to DDR before executing. check configuration in PBI/RCW :

exemple file .rcw:

write 0x57015c, 0x40100000