LS1028: could not attach to PHY

[yuvarajesh_vall]

Hi, 

I have a problem with connecting to Ethernet(SGMII and RGMII) in our custom board based on LS1028.

Please find the output from connecting to SGMII and RGMII below:

root@root:~# ip link set up eth0
[ 344.709641] net eth0: could not attach to PHY
ip: SIOCSIFFLAGS: No such device

root@root:~# ip link set up eth1
[ 397.709310] net eth1: could not attach to PHY

ip: SIOCSIFFLAGS: No such device

The eth dts configuration:

&enetc_port0 {
phy-handle = <&sgmii_phy0>;
phy-connection-type = "sgmii";

mdio {
#address-cells = <1>;
#size-cells = <0>;
sgmii_phy0: ethernet-phy@2 {
reg = <0x2>;
max-speed = <1000>;
// interrupt-parent = <&gpio1>;
// interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};
};
};

&enetc_port1 {
phy-handle = <&rgmii_phy0>;
phy-connection-type = "rgmii";

mdio {
#address-cells = <1>;
#size-cells = <0>;
rgmii_phy0: ethernet-phy@1 {
reg = <0x1>;
max-speed = <100>;
// interrupt-parent = <&gpio1>;
// interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};
};
};

kernel configuration:

# ethernet mdio
CONFIG_FSL_ENETC=y
CONFIG_FSL_ENETC_MDIO=y
CONFIG_FSL_ENETC_VF=y
CONFIG_FSL_ENETC_PTP_CLOCK=y
FSL_ENETC_HW_TIMESTAMPING=y

# Ethernet Gigabit PHY TI
CONFIG_DP83867_PHY=y

# CONFIG_IPV6 is not set

# TSN switch
CONFIG_TSN=y
CONFIG_ENETC_TSN=y

# Microsemi PHY
CONFIG_NET_VENDOR_MICROSEMI=y
CONFIG_MICROSEMI_PHY=y

# Felix Switch
CONFIG_MSCC_OCELOT_SWITCH=y
CONFIG_MSCC_FELIX_SWITCH=y
CONFIG _MSCC_FELIX_SWITCH_TSN=y
CONFIG_MSCC_FELIX_SWITCH_PTP_CLOCK=y

is my devicetree and kernle configuations okay?

Thank you for your help in advance

regards,

Uvi

[yuvarajesh_vall]

Hi Fedor,

Sorry for dts file not attached. Please find the corrected and attached dts file. 

Thank you

[ufedor]

Please provide:

1) connection schematics as searchable PDF

2) complete DTS

[yuvarajesh_vall]

Hi Fedor,

Thank you for your reply.

1) I am not allowed to send the schematics. Our hardware developer tested again with the board(PHY connections). it seems good. 

2) Please find the dts file below:

/*
* Device Tree Include file for Test CPU Board
*
*/

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "fsl-ls1028a.dtsi"

/ {
model = "Test Board";
compatible = "fsl,ls1028a";

aliases {
/* TBD ethernet */
crypto = &crypto;
serial0 = &duart0;
serial1 = &duart1;
};

chosen {
stdout-path = "serial0:115200n8";
};

memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x1 0x0000000>;
};

sys_mclk: clock-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};

reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};

sb_3v3: regulator-sb3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3_vbus";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};

/* Provide gpios from controllers as single gpio with correct label */
gpio_export {
compatible = "gpio-export";

/************************** CPU GPIO-CONTROLLER *************************/

/* GPIO1_22 => GPIO122_I2C1_DEBUGx */

gpio_122_i2c1_debug {
gpio-export,name = "gpio_122";
gpio-export,direction_may_change;
gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
};

/* GPIO1_23 => GPIO123_I2C5_DEBUGx */

gpio_123_i2c5_debug {
gpio-export,name = "gpio_123";
gpio-export,direction_may_change;
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
};

/* GPIO1_26 => GPIO126_JTAG_DEBUG10x */

gpio_126_jtag_debug10 {
gpio-export,name = "gpio_126";
gpio-export,direction_may_change;
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
};

/* GPIO1_27 => GPIO127_JTAG_DEBUG11x */

gpio_127_jtag_debug11 {
gpio-export,name = "gpio_127";
gpio-export,direction_may_change;
gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
};

/* GPIO1_30 => GPIO130_CPU_RXx */

gpio_130_cpu_rx {
gpio-export,name = "gpio_130";
gpio-export,direction_may_change;
gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
};

/* GPIO1_31 => GPIO131_CPU_TXx */

gpio_131_cpu_tx {
gpio-export,name = "gpio_131";
gpio-export,direction_may_change;
gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
};

/* GPIO2_06 => GPIO206_JTAG_DEBUG20x */

gpio_206_jtag_debug20 {
gpio-export,name = "gpio_206";
gpio-export,direction_may_change;
gpios = <&gpio2 06 GPIO_ACTIVE_HIGH>;
};

/* GPIO2_07 => GPIO207_JTAG_DEBUG21x */

gpio_207_jtag_debug21 {
gpio-export,name = "gpio_207";
gpio-export,direction_may_change;
gpios = <&gpio2 07 GPIO_ACTIVE_HIGH>;
};

/* GPIO2_28 => GPIO228_SGMII_INTx */

gpio_228_sgmii_int {
gpio-export,name = "gpio_228";
gpio-export,direction_may_change;
gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
};

/* GPIO2_29 => GPIO229_RGMII_INTx */

gpio_229_rgmii_int {
gpio-export,name = "gpio_229";
gpio-export,direction_may_change;
gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
};

/* GPIO2_30 => GPIO230_QSGMII_INTx */

gpio_230_qsgmii_int {
gpio-export,name = "gpio_230";
gpio-export,direction_may_change;
gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
};

/* GPIO2_31 => GPIO231_CH_IDENTx */

gpio_231_ch_ident {
gpio-export,name = "gpio_231";
gpio-export,direction_may_change;
gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>;
};

/* GPIO3_13 => GPIO313_SC_MUXx */

gpio_313_sc_mux {
gpio-export,name = "gpio_313";
gpio-export,direction_may_change;
gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
};

/* GPIO3_14 => GPIO314_EXT_WD_TRIGx */

gpio_314_ext_wd_trig {
gpio-export,name = "gpio_314";
gpio-export,direction_may_change;
gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
};

/* GPIO3_15 => GPIO315_EXT_WD_DISx */

gpio_315_ext_wd_dis {
gpio-export,name = "gpio_315";
gpio-export,direction_may_change;
gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
};

/* GPIO3_16 => SECURE_BOOT_FAILUREx*/

gpio_316_secure_boot_failure {
gpio-export,name = "gpio_316";
gpio-export,direction_may_change;
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
};

/****************************FIRST IO-EXPANDER ****************************/

/* IO-EXPANDER P00 does not exist */

/* IO-EXPANDER P01 does not exist */

/* IO-EXPANDER P02 does not exist */

/* IO-EXPANDER P03 does not exist */


/* IO-EXPANDER P04 => PCIE_MINICARD_PWRENx */

// pcie_minicard_pwr_en {
// gpio-export,name = "pcie_minicard_pwr_en";
// gpio-export,output = <1>;
// gpio-export,direction = "out";
// gpio-export,direction_may_change;
// gpios = <&io_expander0 4 GPIO_ACTIVE_LOW>;
// };

/* IO-EXPANDER P05 => SECURE_BOOT_FUSE_PROGx */

secure_boot_fuse {
gpio-export,name = "secure_boot_fuse";
gpio-export,output = <0>;
gpio-export,direction = "out";
gpio-export,direction_may_change;
gpios = <&io_expander0 5 GPIO_ACTIVE_HIGH>;
};

/* IO-EXPANDER P06 => PCIE_MINICARD_RESETx */

// pcie_minicard_reset {
// gpio-export,name = "pcie_minicard_reset";
// gpio-export,output = <1>;
// gpio-export,direction = "out";
// gpio-export,direction_may_change;
// gpios = <&io_expander0 6 GPIO_ACTIVE_LOW>;
// };

/* IO-EXPANDER P07 => W_DISABLEx */

w_disable {
gpio-export,name = "w_disable";
gpio-export,output = <1>;
gpio-export,direction = "out";
gpio-export,direction_may_change;
gpios = <&io_expander0 3 GPIO_ACTIVE_LOW>;
};

/****************************SECOND IO-EXPANDER ****************************/

/* IO-EXPANDER P00 => GP_LEDx[0]_GREEN */

gp_led0_green {
gpio-export,name = "gp_led0_green";
gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "none";
};

/* IO-EXPANDER P01 => GP_LEDx[0]_RED */

gp_led0_red {
gpio-export,name = "gp_led0_red";
gpios = <&io_expander1 1 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "none";
};

/* IO-EXPANDER P02 => GP_LEDx[1]_GREEN */

gp_led1_green {
gpio-export,name = "gp_led1_green";
gpios = <&io_expander1 2 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "none";
};

/* IO-EXPANDER P03 => GP_LEDx[1]_RED */

gp_led1_red {
gpio-export,name = "gp_led1_red";
gpios = <&io_expander1 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "none";
};

/* IO-EXPANDER P04 => GP_LEDx[2]_GREEN */

gp_led2_green {
gpio-export,name = "gp_led2_green";
gpios = <&io_expander1 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "none";
};

/* IO-EXPANDER P05 => GP_LEDx[2]_RED */

gp_led2_red {
gpio-export,name = "gp_led2_red";
gpios = <&io_expander1 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "none";
};

/* IO-EXPANDER P06 => GP_LEDx[2]_GREEN */

gp_led3_green {
gpio-export,name = "gp_led3_green";
gpios = <&io_expander1 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "none";
};

/* IO-EXPANDER P07 => GP_LEDx[2]_RED */

gp_led3_red {
gpio-export,name = "gp_led3_red";
gpios = <&io_expander1 7 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "none";
};
};
};

/* Enable Debug UART1 */
&duart0 {
status = "okay";
current-speed = <115200>;
};

/* Enable Debug UART2 */
&duart1 {
status = "okay";
current-speed = <115200>;
};

&i2c0 {
status = "okay";
clock-frequency = <400000>;
enable-workaround;

/* GPIO1-CONTROLLER GPIO1_22 => GPIO122_I2C1_DEBUGx */
gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;

/* I2C I/O-Expander TCA6408A IC67 */

io_expander0: tca6408@20 {
compatible = "ti,tca6408";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x20>;
#gpio-cells = <2>;
};

/* I2C I/O-Expander TCA6408A IC193 */

io_expander1: tca6408@21 {
compatible = "ti,tca6408";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x21>;
#gpio-cells = <2>;
};

/* Temperature sensor TMP461 IC37 */
temp_sensor0: tmp461@48 {
compatible = "ti,tmp401";
reg = <0x48>;
#gpio-cells = <2>;
};

/* NXP RTC PCF85063ATT IC19 */
rtc0: nxp,pcf85063@51 {
compatible = "nxp,pcf85063";
reg = <0x51>;
};

/* SPD 2K EEPROM DDR4 IC21 */
ddr4_eeprom: eeprom@52 {
reg = <0x52>;
};

/* Board Data 2K EEPROM ST-M24SR64 IC57 */
bd_eeprom: eeprom@56 {
reg = <0x56>;
};

/* PCIe Switch PI7C9X2G404SL IC64 */
// pcie: pcie-switch@6f {
/*TODO compatible = ""; */
// reg = <0x6f>;
// };
};

&i2c4 {
status = "okay";
clock-frequency = <100000>;
enable-workaround;

/* GPIO1-CONTROLLER GPIO1_23 => GPIO123_I2C5_DEBUGx */
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;

};
};

/* USB1 (front USB) */
&usb0 {
};

/* USB2 (routed to USB HUB) */
&usb1 {
};

&esdhc {
status = "okay";
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
sd-uhs-sdr12;
};

&esdhc1 {
status = "okay";
cap-sd-highspeed;
cap-mmc-highspeed;
};

#if 0
&fspi {
status = "okay";
w25q128fw: flash@0 {
compatible = "winbond,w25q128fw", "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
reg = <0>;
};
};
#endif

&enetc_port0 {
phy-handle = <&sgmii_phy0>;
phy-connection-type = "sgmii";

mdio {
#address-cells = <1>;
#size-cells = <0>;
sgmii_phy0: ethernet-phy@2 {
reg = <0x2>;
max-speed = <1000>;
// interrupt-parent = <&gpio1>;
// interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};
};
};

&enetc_port1 {
phy-handle = <&rgmii_phy0>;
phy-connection-type = "rgmii";

mdio {
#address-cells = <1>;
#size-cells = <0>;
rgmii_phy0: ethernet-phy@1 {
reg = <0x1>;
max-speed = <100>;
// interrupt-parent = <&gpio1>;
// interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};
};
};

&enetc_mdio_pf3 {
qsgmii_phy1: ethernet-phy@4 {
reg = <0x10>;
max-speed = <100>;
// interrupt-parent = <&gpio1>;
// interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};

qsgmii_phy2: ethernet-phy@5 {
reg = <0x11>;
max-speed = <100>;
// interrupt-parent = <&gpio1>;
// interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};

qsgmii_phy3: ethernet-phy@6 {
reg = <0x12>;
max-speed = <1000>;
// interrupt-parent = <&gpio1>;
// interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};

qsgmii_phy4: ethernet-phy@7 {
reg = <0x13>;
max-speed = <100>;
// interrupt-parent = <&gpio1>;
// interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};
};

/* l2switch ports */
&switch_port0 {
phy-handle = <&qsgmii_phy1>;
phy-connection-type = "qsgmii";
};

&switch_port1 {
phy-handle = <&qsgmii_phy2>;
phy-connection-type = "qsgmii";
};

&switch_port2 {
phy-handle = <&qsgmii_phy3>;
phy-connection-type = "qsgmii";
};

&switch_port3 {
phy-handle = <&qsgmii_phy4>;
phy-connection-type = "qsgmii";
};

&can0 {
status = "okay";
};

&can1 {
status = "okay";
};

&display0 {
status = "disabled";
};

&sata {
status = "disabled";
};

Thank you in advance

Uvi

[ufedor]

It is always reasonable to provide files as attachments and not inline.

Provided DTS seems to be incomplete - it lacks at least one closing "}".

Please try to generate LSDK composite firmware as described in the Layerscape Software Development Kit User Guide.