LS1020A RCW clock settings for QuadSPI Boot

[christopheniclaes]

I've a new custom board with LS1020A.

I'm trying to create the right RCW data using Processor Expert in Codewarrior for QorIQ LS Series ARM V7 ISA v10.0.9 (latest available now).

Basic board description:

- SYSCLK = 100 MHz

- I want 800MHz for Core

- I want 300 MHz for platform

- I want 1300 MT/s for DDR3L

- I want the PBL to use QuadSPI Flash

Using the PBL generator, I did this configuration:

- SYS_PLL_RAT = 3 -> 3X

- MEM_PLL_RAT = 13 -> 13X

- CGA_PLL1_RAT = 8 -> 8X

- C1_PLL_SEL = "0" -> PLL1/1

- DDR_FDBK_MUL = "10" -> Effective DDRL PLL multiplication = MEM_PLL_RAT

This configuration is rejected by PBL generator with a message "The qSPI interface does not work at this frequency since maximum frequency for qSPI is 62.5 MHz as noted in the datasheet.

The input clock to the qSPI block (cluster1 clk) is 800 MHz with this configuration. the qSPI clock is, by default, divided by 256 by the reset value of SCFG_QSPI_CFG, so 800/256=3.125MHz. The PBL generator show a qSPI frequency of 100MHz, and I don't undestand where this value come from.

Question 1: is there bug in Processor Expert regarding qSPI clock check? Any idea?

Question 2: as the PBI commands are used to setup SCFG_QSPI_CFG before booting, why is there a check on this qSPI frequency?

Question 3:  in the LS1021A reference manual, there is a remark:

"For less than 1 GHz operation: The value of this field should be twice the required core clock frequency and C1_PLL_SEL should be set to 4’b0001 (CGA_PLL1/2). For example, to achieve 800 MHz core clock frequency with reference clock frequency of 100 MHz, the ratio should be 16 (0x10) for locking the CGA PLL1 at 1600 MHz and C1_PLL_SEL=4’b0001 to achieve 800 MHz core clock frequency."

This constraint is not fullfilled with the first configuration, so I can update it like that:

- SYS_PLL_RAT = 3 -> 3X

- MEM_PLL_RAT = 13 -> 13X

- CGA_PLL1_RAT = 16 -> 16X

- C1_PLL_SEL = "1" -> PLL1/2

- DDR_FDBK_MUL = "10" -> Effective DDRL PLL multiplication = MEM_PLL_RAT

Could you explain why there is this constraint? What would be the consequence not fullfilling it ? PLL Stability? Power Consumption?

Question 4: the existing RCW files for LS1021ATWR qSPI boot contain this command:

write 0x57015c, 0x00000803

It is related to SCFG_QSPI_CFG value with the divider stored in the 4 high-order bits.The particular value shown is 0000 which mean divide by 256 as decribed in the reference manual.

Why is there non-null data in the 12 low-order bits (0x803) which are marked as reserved in the Reference Manual? Is it mandatory ? Where is it documented?

Thanks for support!

Christophe Niclaes

[yipingwang · Accepted solution]

In CodeWarrior IDE, please click "Vew Menu" icon, then select "Ignore Constraints and non-Critical Errors" option, please refer to my attached screenshot, then you could create PBL binary by "generate code".

 I checked the latest LS1020A reference manual, didn't find the highest frequency of QSPI IF of LS1021A family was 62.5 MHz. According to the comment from the QCVS tool team, this should be a defect of the tool.