Does LS2084ardb only support 10gbase-kr for Backplane mode

[howard12005]

Hi,

I have a customized LS2084ARDB Board, 

I use Marvell switch 88E6191X 10G Port connect to Serdes1 10gbase-kr,

but there is a ping CPU port fail with the connection in uboot.

NXP FAE recommends that we refer to the AN12572 spec to set 10gbase-kr,

I would like to ask whether the support of 10Gbase-kr is only applicable to Backplane mode??

Is it necessary to set link_type = "MAC_LINK_TYPE_BACKPLANE" in dpc dts?

board_info {
ports {
…
mac@1 {
link_type = "MAC_LINK_TYPE_BACKPLANE";
             };
           …
             };
       };
};

[howard12005]

Hi,Thanks Reply

I mean the location of mc_fw offset load,

like your link, It was supposed to be the first item load, but failed, so load the second item can also succeed,

1. QSPI location space

0x0000_2000_0000

0x0000_2FFF_FFFF

256MB

Quad SPI Region #1 (0-256MB)

More QSPI space below 256MB

2. DRAM location space

0x0000_8000_0000

0x0000_9FFF_FFFF

512MB

GPP DRAM Region #1 (0-2GB)

Finally, dpmac is initialized successfully, and can ping mac IP in kerenl,
But always show this message: fsl-mc: Deploying data path layout ... WARNING: Firmware returned an error (GSR: 0x3f)

PCIe0: pcie@3400000 disabled
PCIe1: pcie@3500000 Root Complex: x4 gen3
PCIe2: pcie@3600000 Root Complex: no link
PCIe3: pcie@3700000 Root Complex: no link
DPMAC1@xgmii [PRIME]
SF: Detected mx25u6435f with page size 256 Bytes, erase size 64 KiB, total 8 MiB
device 0 offset 0x400000, size 0x300000
SF: 3145728 bytes @ 0x400000 Read: OK
device 0 offset 0x620000, size 0x100000
SF: 1048576 bytes @ 0x620000 Read: OK
crc32+
fsl-mc: Booting Management Complex ... SUCCESS
fsl-mc: Management Complex booted (version: 10.18.0, boot status: 0x1)
Hit any key to stop autoboot: 0
Switch 88E6191X all ports enable.
=> run bootcmd_nvme0

Device 0: Vendor: 0x1e95 Rev: 1.01 Prod: 0020341Y000K
Type: Hard Disk
Capacity: 122104.3 MB = 119.2 GB (250069680 x 512)
... is now current device
Scanning nvme 0:1...
Scanning nvme 0:2...
Found U-Boot script /ls2088ardb_boot.scr
961 bytes read in 0 ms
## Executing script at 80000000
22198280 bytes read in 25 ms (846.8 MiB/s)
32048 bytes read in 1 ms (30.6 MiB/s)
## Flattened Device Tree blob at 90000000
Booting using the fdt blob at 0x90000000
Loading Device Tree to 000000009fff5000, end 000000009ffffd2f ... OK
fsl-mc: Deploying data path layout ... WARNING: Firmware returned an error (GSR: 0x3f)

Starting kernel ...

[howard12005]

Hi,

Thanks, After initializing the marvell switch 10G serdes, can successfully ping to the cpu port
It means that the nxp cpu end to the marvell switch is connected in uboot

I will follow BACKPLANE mode to set the kernel dts, since serdes1 only uses 10gbase-kr pcs_mdio1,

1. then I need to disable emdio1 emdio2 in kernel dts?

2. I use QSPI flash to boot, and then mc, dpc, dpl firmware load dram space is successful, but load qspi space failed

    I refer to the LSDK code is default load qspi space, load dram space will this affect the dpaa2 ethernet connection?

&emdio1 {

    status = "disabled";

};

&emdio2 {

    status = "disabled";

};

&pcs_mdio1 {

        pcs_phy1: ethernet-phy@0 {

        backplane-mode = "10gbase-kr";

        compatible = "ethernet-phy-ieee802.3-c45";

        reg = <0xa>;

        fsl,lane-handle = <&serdes1>;

        fsl,lane-reg = <0x9C0 0x40>;/* lane H */

    };

};

[bpe]

I'm not sure I understand your recent inputs. If you are having problems with
QSPI boot, please be sure to create a new thread or Support Case. I can only
tell that MC firmware, DPL and DPC binaries must be available at the addresses
specified in the corresponding arguments to fsl_mc u-Boot command when this
command is invoked. More details can be found in LSDK online documentation

https://docs.nxp.com/bundle/GUID-C3A436DA-E944-4F73-9811-2335DEBD04D6/page/GUID-81E61F39-077D-4384-9...

and u-Boot source code:

https://source.codeaurora.org/external/qoriq/qoriq-components/u-boot/tree/drivers/net/fsl-mc/mc.c

Best Regards,
Platon

[bpe]

Trust your FAE. Specifically for backplane-type connection and 10Gbps data rate,
10Gbase-KR is the only supported mode. Other 10Gbps SerDes modes require the
connected device to be a PHY or a device that behaves identically to a 10G PHY
and can be automatically recognized as such.

Section 2.2 of AN12572 clearly mentions that modifications to DPC are mandatory
for all DPAA2-based processors. LS2084 does belong to this category.

If the link does no work, the suggestions are:

• Check with the documentation of device you connected that it does support 10GBase-KR
  and is properly configured for that.
• Analyse the statistics at LS2084A side to have an idea of what is wrong.
  Follow AN12572 Section 4 to read the interface statistics information.

Hope this helps,
Platon