Hello,
I am in the process of configuring the DDR controller registers for an LS1043/23 based board using the CodeWarrior DDR tool, and I have a question regarding the DQ_MAP registers.
I have two 16 bit DRAM chips that are used to form the 32 bit bus. DQ0-DQ15 are on the first chip, and DQ16-DQ31 are on the second chip.
Suppose the design has a 1-to-1 correlation of DRAM chip DQ pins to processor DQ pins (so no swizzling). In other words, DQ0 of the DRAM chip goes to MDQ0 of the processor, DQ4->MDQ4, DQ8->MDQ8, all the way up to DQ28->MDQ28 and DQ31->MDQ31.
Would this mean that the DQ_MAP registers need to all be set to 0? This is what they are set to on the LS1043ardb target config files, and according to the schematic for the LS1043ardb, it's also wired 1-to-1.
However, reading the datasheet, it seems like the values should actually be 0x01 and 0x21 for the lower and upper nibble of each byte lane respectively.
A value of 0x01 for the lower nibble maps DRAM DQ0->MDQ0, DQ1->MDQ1, DQ2->MDQ2, and DQ3->MDQ3.
And a value of 0x21 for the upper nibble maps DRAM DQ4->MDQ4, DQ5->MDQ5, DQ6->MDQ6, and DQ7->MDQ7.
Am I understanding this correctly?
How is it that the LS1043ardb eval board target config file is able to work with DQ_MAP values of all 0?
