Confirmation if it is OK to use reserved values for IFC timing registers in normal GPCM mode?

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

Confirmation if it is OK to use reserved values for IFC timing registers in normal GPCM mode?

ソリューションへジャンプ
1,873件の閲覧回数
sinasattari
Contributor II

We have custom board designed based upon #QorIQ LS1021A ARM CPU. In the reference manual it lists the following reserved values for #IFC GPCM mode:

TACSE of IFC_FTIM0_CSn_GPCM =000:Reserved
TACO of IFC_FTIM1_CSn_GPCM =00000000:Reserved
TCS of IFC_FTIM0_CSn_GPCM =0000:Reserved 

but at the same time there is a note explaining (page 1590):

For normal GPCM mode (write transaction) all the three timing parameters (that is, TEAHC, TACSE, and TCS) should not be programmed zero together.
• For normal GPCM mode (read transaction) all the three timing parameters (that is, TEAHC, TACSE, and TACO) should not be programmed zero together.

In our setup, we have:

TEAHC =0x1 , TACSE= 0x0, and TCS = 0x0 for write

TEAHC =0x1 , TACSE= 0x0, and TACO= 0x0 for read. 

The system is working correctly, however I wanted to get confirmation that it is OK to use "reserved" zero settings for TACSE and TCS and TACO as long as they are not all set to zero simultaneously.

ラベル(1)
タグ(1)
0 件の賞賛
返信
1 解決策
1,640件の閲覧回数
Pavel
NXP Employee
NXP Employee

Usually designers do not recommend using reserved values. It can produce unpredictable behavior. Designers usually do not tested behavior if reserved values are used.


Have a great day,
Pavel Chubakov

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

元の投稿で解決策を見る

0 件の賞賛
返信
3 返答(返信)
1,641件の閲覧回数
Pavel
NXP Employee
NXP Employee

Usually designers do not recommend using reserved values. It can produce unpredictable behavior. Designers usually do not tested behavior if reserved values are used.


Have a great day,
Pavel Chubakov

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 件の賞賛
返信
1,640件の閲覧回数
Pavel
NXP Employee
NXP Employee

The LS1021a Reference Manual is correct.

For normal GPCM mode (write transaction) all the three timing parameters (that is, TEAHC, TACSE, and TCS) should not be programmed zero together.

For normal GPCM mode (read transaction) all the three timing parameters (that is, TEAHC, TACSE, and TACO) should not be programmed zero together.

 

See attached file. It is u-boot configuration file for the TWR-LS1021a board. Find the CONFIG_SYS_NOR_FTIM0 setting in this file.


Have a great day,
Pavel Chubakov

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 件の賞賛
返信
1,640件の閲覧回数
sinasattari
Contributor II

Thank you Pavel for your reply.

I checked the file and actually we started from #LS1021ATWR as our reference design.

I wanted to make sure it is OK to use reserved value 0 for TEAHC, TACSE, TCS and TACO as long as they are not all zeros in grouping mentioned in the manual.

Best Regards,

Sina Sattari

0 件の賞賛
返信