- Forums
- Product Forums
- General Purpose MicrocontrollersGeneral Purpose Microcontrollers
- i.MX Forumsi.MX Forums
- QorIQ Processing PlatformsQorIQ Processing Platforms
- Identification and SecurityIdentification and Security
- Power ManagementPower Management
- MCX Microcontrollers
- S32G
- S32K
- S32V
- MPC5xxx
- Other NXP Products
- Wireless Connectivity
- S12 / MagniV Microcontrollers
- Powertrain and Electrification Analog Drivers
- Sensors
- Vybrid Processors
- Digital Signal Controllers
- 8-bit Microcontrollers
- ColdFire/68K Microcontrollers and Processors
- PowerQUICC Processors
- OSBDM and TBDML
- S32M
-
- Solution Forums
- Software Forums
- MCUXpresso Software and ToolsMCUXpresso Software and Tools
- CodeWarriorCodeWarrior
- MQX Software SolutionsMQX Software Solutions
- Model-Based Design Toolbox (MBDT)Model-Based Design Toolbox (MBDT)
- FreeMASTER
- eIQ Machine Learning Software
- Embedded Software and Tools Clinic
- S32 SDK
- S32 Design Studio
- GUI Guider
- Zephyr Project
- Voice Technology
- Application Software Packs
- Secure Provisioning SDK (SPSDK)
- Processor Expert Software
- MCUXpresso Training Hub
-
- Topics
- Mobile Robotics - Drones and RoversMobile Robotics - Drones and Rovers
- NXP Training ContentNXP Training Content
- University ProgramsUniversity Programs
- Rapid IoT
- NXP Designs
- SafeAssure-Community
- OSS Security & Maintenance
- Using Our Community
-
- Cloud Lab Forums
-
- Knowledge Bases
- ARM Microcontrollers
- i.MX Processors
- Identification and Security
- Model-Based Design Toolbox (MBDT)
- QorIQ Processing Platforms
- S32 Automotive Processing Platform
- Wireless Connectivity
- CodeWarrior
- MCUXpresso Suite of Software and Tools
- MQX Software Solutions
-
- Home
- :
- ARM Microcontrollers
- :
- LPCware Archive Content
- :
- IOH Libraries
IOH Libraries
- Subscribe to RSS Feed
- Mark as New
- Mark as Read
- Bookmark
- Subscribe
- Printer Friendly Page
- Report Inappropriate Content
IOH Libraries
IOH Libraries
Introduction
This page gives a quick overview of the available IOH libraries. A description of the library, its specifications and its requirements are summarized on this page.
The the following downloads are attached to the community post below.
- Full library documentation.
- The IOH pre-compiled libraries.
- 1 or more application example source-code/projects per library (LPCXpresso, Keil MDK, IAR EWARM).
The following libraries are currently available:
- Serial-interface emulation
- DALI
- I2S master
- I2C master
- UART
- CPU-cycle saving libraries
- CRC
- Windowed Comparator
- DMA
The serial-interface emulation allows easy addition of one more serial interface to the LPC11x37H microcontrollers.The CPU-cycle saving libraries offer CPU-offloading for certain tasks, which can be used for lower power consumption (ARM core put in sleep mode), or for high performance (ARM executing other tasks in parallel).
DALI
The I/O Handler DALI library provides functionality to emulate a DALI master using the I/O Handler hardware block. DALI is a technical standard for network-based systems that control lighting in e.g. building automation. The IOH library allows to handle a large portion of the DALI standard autonomously by the I/O Handler peripheral with zero to very little CPU load.The library integrates a large portion of the DALI interface. The easy-to-use API is non-blocking and only passes the data to be transmitted to the I/O Handler.After a transfer has been initiated, the I/O handler takes care of the Manchester encoding and generation of edges on an I/O pin without any CPU involvement. The IOH ensures the mandatory wait time (settling time) between frames is honored and keeps track of the DALI input pin to watch for any response. Besides the supported polling mode to test if a transmission has finished, an interrupt is also generated at the end of every transmission. Data indicating whether the slave has send back a response and what this response is, can be accessed through another API call.
Specifications
- Master mode only (a future library update may add slave support).
- Manchester encoding/decoding, pin I/O and settling time all handled by IOH with zero CPU load.
- Support for both polling mode and interrupt mode.
- Configurable Rx/Tx polarity. This allows using both inverting and non-inverting DALI bus drivers.
Requirements
- Library is designed for the LPC11E37H and the LPC11U37H.
- Requires 1.5kB Flash storage.
- Counter/timer module CT16B1 is used by IOH and is no longer available to the ARM core.
Pinning
| DALI Function | Description | Pin |
| TxD | DALI transmit data output | PIO1_6/IOH_16 |
| RxD | DALI receive data input | PIO1_7/IOH_17 |
I2S master
The I/O Handler I2S library allows emulation of a basic I2S master (transmit only). I2S (Inter-IC Sound) is an electrical serial bus interface standard used for connecting digital audio devices together. It is used to communicate PCM audio data between integrated circuits in an electronic device. The IOH library allows emulation of a basic I2S master while not loading the CPU heavily with this task. The required CPU activity for this task is limited to ensure the data is available in the buffer in time for IOH to read it.After configuring and starting the I2S emulation, the I/O Handler continuously reads a 1kB data buffer and transmitting this buffer over the emulated I2S interface. After reading/transmitting the entire buffer, it wraps-around and begins reading/transmitting from the top of the buffer, thereby creating a continuous stream of data. An interrupt is asserted every time when the first half of the buffer has been read, and when the second half of the buffer has been read. This allows the CPU to fill the half of the buffer which is not being accessed by IOH with new data.
Specifications
- Master mode only.
- Configurable for either I2S transmit or receive functionality (simultaneous transmit/receive not supported).
- 2 channels, 16-bit per channel.
- Loops over a 1kB data array.
Requirements
- Library is designed for the LPC11E37H and the LPC11U37H.
- Requires 1kB Flash storage.
- Requires usage of one of any of the available timer modules (CT16B0, CT16B1, CT32B0 or CT32B1). Selected timer module is no longer available to the ARM core.
Pinning
| I2S Function | Description | Pin |
| SCL | I2S bit-clock | Any external match output pin of the selected timer (e.g. CT16B1_MAT0, CT32B0_MAT3, etc) |
| WS | I2S word-select output | Configurable, following pins can be selected: IOH[7:0] |
| TX_SDA | I2S data output | Configurable, following pins can be selected: IOH[7:0] |
| RX_SDA | I2S data input | Configurable, following pins can be selected: PIO1_5/IOH_15 or PIO1_6/IOH_19 |
| SCL_In | I2S bit-clock input (requires to be connected externally to the SCL signal) | Configurable, following pins can be selected: PIO0_8/IOH_6, PIO1_6/IOH_16 or PIO1_27/IOH_20 |
I2C master
The I/O Handler I2C library provides functionality to emulate an I2C master using the I/O Handler hardware block. The I2C bus was designed by Philips in the early ‘80s to allow easy communication between components which reside on the same circuit board. The IOH library allows I2C communication fully handled by IOH, with zero CPU load after a transfer has been initiated. The easy-to-use API is non-blocking and only passes the data to be transmitted to the I/O Handler.After a transfer has been initiated, the I/O Handler handles the full I2C transfer with zero CPU-load. The IOH interrupt is asserted when a transfer has been completed. The API supports functions like I2C write, I2C read and I2C read/write.
Specifications
- Master mode only.
- Repeated start supported.
- Clock stretching supported.
- Bit rate up to 300Kbps for 48MHz CPU clock.
- Support for both polling mode and interrupt mode.
- Multi-master not supported.
- 10-bit address not supported.
Requirements
- Library is designed for the LPC11E37H and the LPC11U37H.
- Requires 1.5kB Flash storage.
- Counter/timer module CT16B1 is used by IOH and is no longer available to the ARM core.
Pinning
| I2C Functions | Description | Pin |
| SDA | I2C data input/output | Configurable, following pins can be selected: PIO1_[31:0] |
| SCL | I2C clock output | Configurable, following pins can be selected: PIO1_[31:0] |
UART
The I/O Handler UART library provides functionality to emulate a UART using the I/O Handler hardware block. The implemented UART is capable of full-duplex communication at common UART formats (7/8 databits, 1/2 stopbits), and with a configurable baud rate (up to 115200 baud). Flow control through hardware handshaking is supported (RTS/CTS). Receive and transmit FIFOs are configurable, and interrupts are generated based on FIFO thresholds. A low-level API offers receive and transmit primitives, as well as interrupt events. A sample driver demonstrates how to use this to create buffered I/O.
Specifications
- Asynchronous, full-duplex.
- Baud rates up to 115200 for 48 MHz CPU clock.
- Data formats 7N1, 7N2, 8N1, 8N2.
- Hardware handshaking: CTS controlled by I/O Handler, RTS controlled by driver software.
Requirements
- Library is designed for the LPC11E37H and the LPC11U37H.
- Requires 1.25 KiB Flash storage.
- Counter/timer module CT16B1 is used by IOH and is no longer available to the ARM core.
Pinning
| UART Function | Description | Pin |
| TXD | UART transmit data output | Freely selectable from the 21 possible I/O Handler pins IOH_0…IOH_20 |
| RXD | UART receive data input | Can be selected from the following three pins: PIO0_8/IOH_6, PIO1_6/IOH_16, PIO1_27/IOH_20 |
| CTS | UART clear-to-send input | Freely selectable from the 21 possible I/O Handler pins IOH_0…IOH_20. This signal is optional. |
CRC
The I/O Handler CRC library enables the I/O Hander hardware block as a CRC engine. A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage device to detect accidental changes to raw data. The IOH library allows CRC calculation to be performed by the I/O Handler peripheral with zero CPU load. Through the easy-to-use, non-blocking API of the library the emulated CRC engine can be configured, started and stopped.After a CRC calculation has been initiated, the IOH calculates the CRC over the raw data block with zero CPU load. When the calculation has finished, the IOH interrupt is asserted and the result of the calculation can be read through an API call.
Specifications
- Supported polynomials:
- CRC-16-CCITT (x16 + x12 + x5 + 1)
- CRC-16-IBM (x16 + x15 + x2 + 1)
- Big endian and little endian data supported.
- Configurable seed.
- Support for both polling mode and interrupt mode.
Requirements
- Library is designed for the LPC11E37H and the LPC11U37H.
- Requires 1kB Flash storage.
Windowed Comparator
The IOH windowed comparator allows monitoring up to 4 analog channels with zero CPU load. The ADC continuously converts all enabled channels, while IOH compares the converted values against a per-channel configurable window (consisting of an upper-limit and a lower-limit). When the converted value of any of the enabled channels is outside this window, an interrupt is generated. This task is fully handled by IOH at zero CPU load, meaning that in the meantime the ARM core can be put in sleep mode or execute other tasks. This provides a way to either lower the power consumption (ARM in sleep mode), or enhance performance (ARM executing other tasks).
Specifications
- Converts up to all 8 available analog channels.
- Channel 0-3 can be selected for windowed comparator function.
- Interrupt is generated whenever any of the enabled comparator channels exceeds their window.
- True zero CPU-load.
Requirements
- Library is designed for the LPC11E37H and the LPC11U37H.
- Requires 1.8kB Flash storage.
- ADC module is used by IOH and is no longer available to the ARM core. Note: Conversion result of enabled ADC channels available through API.
