U0ier register offset lpc1114

[lpcware]

Content originally posted in LPCWare by ISTVAN on Sat Jul 09 11:33:34 MST 2011
[FONT=Calibri]The LPC1114 User Manual (UM10398   Rev. 1 - 21 July 2010) on page 102, Table 114 indicates the [B]U0IER[/B] register address offset is 0x004 [/FONT]
[FONT=Calibri](see: [FONT=Calibri]U0IER R/W [B][COLOR=red]0x004[/COLOR][/B] Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts.)[/FONT][/FONT]


[FONT=Calibri][FONT=Calibri]The LPC11xx.h file from the Example Projects has the IER offset at [COLOR=red]0x000[/COLOR] [/FONT][/FONT]
[FONT=Calibri][FONT=Calibri](see: [/FONT][/FONT][COLOR=#3f7f5f][FONT=Courier New]/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/[/FONT][/COLOR]
[COLOR=#3f7f5f][FONT=Courier New]/** @[U]addtogroup[/U] LPC11xx_UART LPC11xx Universal Asynchronous Receiver/Transmitter [/FONT][/COLOR]
[COLOR=#3f7f5f][FONT=Courier New]@{[/FONT][/COLOR]
[COLOR=#3f7f5f][FONT=Courier New]*/[/FONT][/COLOR]
[B][COLOR=#7f0055][FONT=Courier New]typedef[/FONT][/COLOR][/B][B][COLOR=#7f0055][FONT=Courier New]struct[/FONT][/COLOR][/B]
[COLOR=black][FONT=Courier New]{[/FONT][/COLOR]
[B][COLOR=#7f0055][FONT=Courier New]union[/FONT][/COLOR][/B][COLOR=black][FONT=Courier New] {[/FONT][/COLOR]
[COLOR=black][FONT=Courier New]__I [/FONT][/COLOR][COLOR=#005032][FONT=Courier New]uint32_t[/FONT][/COLOR][COLOR=#0000c0][FONT=Courier New]RBR[/FONT][/COLOR][COLOR=black][FONT=Courier New]; [/FONT][/COLOR][COLOR=#3f7f5f][FONT=Courier New]/*!< Offset: 0x000 Receiver Buffer Register (R/ ) */[/FONT][/COLOR]
[COLOR=black][FONT=Courier New]__O [/FONT][/COLOR][COLOR=#005032][FONT=Courier New]uint32_t[/FONT][/COLOR][COLOR=#0000c0][FONT=Courier New]THR[/FONT][/COLOR][COLOR=black][FONT=Courier New]; [/FONT][/COLOR][COLOR=#3f7f5f][FONT=Courier New]/*!< Offset: 0x000 Transmit Holding Register ( /W) */[/FONT][/COLOR]
[COLOR=black][FONT=Courier New]__IO [/FONT][/COLOR][COLOR=#005032][FONT=Courier New]uint32_t[/FONT][/COLOR][COLOR=#0000c0][FONT=Courier New]DLL[/FONT][/COLOR][COLOR=black][FONT=Courier New]; [/FONT][/COLOR][COLOR=#3f7f5f][FONT=Courier New]/*!< Offset: 0x000 Divisor Latch LSB (R/W) */[/FONT][/COLOR]
[COLOR=black][FONT=Courier New]};[/FONT][/COLOR]
[B][COLOR=#7f0055][FONT=Courier New]union[/FONT][/COLOR][/B][COLOR=black][FONT=Courier New] {[/FONT][/COLOR]
[COLOR=black][FONT=Courier New]__IO [/FONT][/COLOR][COLOR=#005032][FONT=Courier New]uint32_t[/FONT][/COLOR][COLOR=#0000c0][FONT=Courier New]DLM[/FONT][/COLOR][COLOR=black][FONT=Courier New]; [/FONT][/COLOR][COLOR=#3f7f5f][FONT=Courier New]/*!< Offset: 0x004 Divisor Latch MSB (R/W) */[/FONT][/COLOR]
[COLOR=black][FONT=Courier New]__IO [/FONT][/COLOR][COLOR=#005032][FONT=Courier New]uint32_t[/FONT][/COLOR][COLOR=#0000c0][FONT=Courier New]IER[/FONT][/COLOR][COLOR=black][FONT=Courier New]; [/FONT][/COLOR][COLOR=#3f7f5f][FONT=Courier New]/*!< Offset: [COLOR=red][B]0x000[/B][/COLOR] Interrupt Enable Register (R/W) */[/FONT][/COLOR]
[COLOR=black][FONT=Courier New]}; ... etc[/FONT][/COLOR]
[COLOR=#3f7f5f][FONT=Courier New]/*@}*/[/FONT][/COLOR][COLOR=#3f7f5f][FONT=Courier New]/* end of group LPC11xx_UART */[/FONT][/COLOR]

[FONT=Calibri][FONT=Calibri])[/FONT][/FONT]

[FONT=Calibri][FONT=Calibri]I am still setting up and didn&#8217;t have the chance to run the example code [B]uart.c[/B] to see if configuring the UART interrupt works. [/FONT][/FONT]

[FONT=Calibri][FONT=Calibri]Can anyone comment on this? [/FONT][/FONT]

[FONT=Calibri][FONT=Calibri]thanks - Istvan[/FONT][/FONT]

[lpcware]

Content originally posted in LPCWare by ISTVAN on Sat Jul 09 13:07:09 MST 2011
[FONT=Calibri]Thanks for the quick reply.[/FONT]

[lpcware]

Content originally posted in LPCWare by Rob65 on Sat Jul 09 11:58:41 MST 2011
chips ...
now I see the 0x0000 in the comment ...
Indeed a typo - if this was the only one I would be quite happy :eek:

[lpcware]

Content originally posted in LPCWare by Ex-Zero on Sat Jul 09 11:55:48 MST 2011
This is a typo in *.h file :eek:

Of course the offset is 0x004 in this union  :)

[lpcware]

Content originally posted in LPCWare by Rob65 on Sat Jul 09 11:54:26 MST 2011
Can you explain how you see IER at offset 0 ?
I clearly see an offset of 4.
The first member is a union of RBR/THR and DLL, the second member is DLM with IER.

I can confirm that the LPC13xx.h and LPC17xx.h contain the exact same structure and I have used the uart on both devices without any problems.

Rob