LPC1115 and Polling Demo Stops at PLL lock

[lpcware]

Content originally posted in LPCWare by drudolf on Tue Jul 09 08:18:54 MST 2013
I am trying to go through the quickstart design and just load and verify the Polling design for the LPC1115 and PNEV512B boards. Following the steps in AN11308. When running the supplied design in debug mode I hit a break at line 372 in system_LPC11xx.c every time I run it :


341  switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
342    case 0:                    /* Internal RC oscillator             */
343      SystemCoreClock = __IRC_OSC_CLK;
344      break;
345    case 1:                   /* Input Clock to System PLL          */
346      switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
347          case 0:              /* Internal RC oscillator             */
348            SystemCoreClock = __IRC_OSC_CLK;
349            break;
350          case 1:              /* System oscillator                  */
351            SystemCoreClock = __SYS_OSC_CLK;
352            break;
353          case 2:             /* WDT Oscillator                     */
354            SystemCoreClock = wdt_osc;
355            break;
356          case 3:             /* Reserved                           */
357            SystemCoreClock = 0;
358            break;
359      }
360      break;
361    case 2:                   /* WDT Oscillator                     */
362      SystemCoreClock = wdt_osc;
363      break;
364    case 3:                  /* System PLL Clock Out               */
365      switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
366          case 0:           /* Internal RC oscillator             */
367            if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
368              SystemCoreClock = __IRC_OSC_CLK;
369            } else {
370              SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
371            }
[B]372[/B]            break;
373          case 1:             /* System oscillator                  */
374            if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
375              SystemCoreClock = __SYS_OSC_CLK;
376            } else {
377              SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
378            }
379            break;


Any help on debugging this would be appreciated. This is the first time I have run the tools and these are new boards. No mods done to code or boards. Thanks.

[lpcware]

Content originally posted in LPCWare by cwpjr on Wed Jul 17 10:54:34 MST 2013
In my experience your don't have a valid clock selected for input to the pll. it will never stabilize without an input clock.

My NXP 1114 board has an external 12mhz crystal and the CMSIS layer code for my board/chip (unmodified), the code you site here, chooses the external xtal, even though it's the same frequency as the internal clock.

2cents, hope it helps!