LPC_SC->DMAREQSEL |= 1; //Select REQ source Timer0, Mat0.0 LPC_SC->PCONP |= (1 << 29);//Power up GPDMA LPC_GPDMA->DMACConfig |= 1;//Enable GPDMA Controller LPC_TIM0->IR = 0x0f; //clear mr, cr LPC_GPDMACH0->DMACCSrcAddr= (uint32_t) &(LPC_GPIO2->FIOPIN); LPC_GPDMACH0->DMACCDestAddr= (uint32_t) &dest[0]; LPC_GPDMACH0->DMACCLLI= 0; LPC_GPDMACH0->DMACCControl= SAMPLE_NUM | (0 << 12)//source burst size - 1 | (0 << 15)//destination burst size - 1 | (0 << 18)//source width - 8bit | (0 << 21)//dest width - 8bit | (0 << 24) | (0 << 25) | (0 << 26)//source increment - do not inc | (1 << 27)//destination increment - inc | (0 << 28) | (0 << 29) | (0 << 30) | (1 << 31);//terminal count interrupt - enabled LPC_GPDMA->DMACIntTCClear |= 1; //Clear CH0 TC Int. flag NVIC_EnableIRQ(DMA_IRQn); LPC_GPDMACH0->DMACCConfig = 1 //Channel Enabled | ((8 & 0x1f) << 1)//source peripheral - MAT0.0 | (0 << 6)//dest request peripheral - none | (2 << 11)//flow control - peripheral to memory | (1 << 14)//(14) - mask out error interrupt | (1 << 15)//(15) - mask out terminal count interrupt | (0 << 16)//(16) - no locked transfers | (0 << 18);//(27) - no HALT |