Content originally posted in LPCWare by PhilYoung on Sat Oct 20 16:20:18 MST 2012
the uart fifo helps reduce the interrupt service rate required, but it is a broken design since there is no mechanism to determine how many characters are in the fifo.
Now I generally use a timer to service the uart and fill the uart fifo, knowing that when I get called again it will be empty. You can try to be clever and use a more frequent timer isr then track when you last wrote to the fifo to work out how much space will be in it.
using THRE will require a faster interrupt, i.e. less than 1 char transmit time if you want to use the full bandwidth of the uart.
If you use THRE, you should always write a character then check THRE again in case you can write a second character before returning as the first character may be transferred immediately to the transmit register if it was empty.
Interrupts for uarts are a pain as you have to handle the case when there is nothing transmitting as not interrupt will be generated, so when you write to the SW fifo you also need to test THRE and service the uart, but do this with interrupts disabled of course.
