Content originally posted in LPCWare by Rorrik on Wed Nov 12 13:15:14 MST 2014 I'm trying to set VTOR on my LPC812, but the best sytax I can come up with for this is:
SCB->VTOR = (0x1000);
But I get an error that SCB doesn't have a member named VTOR. While the user manual says you can use it in Section 3.3.3, and it references the ARMv6-M Architecture Reference Manual, which also seems to imply that the VTOR is implemented, this forum topic says you cannot change the VTOR in Cortex-M0, or in ARMv6.
So, 1) Can I change the VTOR on my device? 2) What would the syntax actually be for accessing this register?
Content originally posted in LPCWare by mc on Sat Jan 17 07:27:00 MST 2015 Yes that is correct . see Page 5/485 of UM10800 Rev. 1(LPC82x). -------------------------------------------------------------------------------------------------------------- 1.4.1 ARM Cortex-M0+ core configuration
The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz. Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two watch points. The ARM Cortex-M0+ core supports a single-cycle I/O enabled port (IOP) for fast GPIO access at address 0xA000 0000. The ARM Cortex M0+ core version is r0p1. The core includes a single-cycle multiplier and a system tick timer (SysTick). ---------------------------------------------------------------------------------------------------------------
see Page 9/370 UM10601(LPC81x) rev1.6
1.5.1 ARM Cortex-M0+ core configuration The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz. Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two watch points. The ARM Cortex-M0+ core supports a single-cycle I/O enabled port (IOP) for fast GPIO access at address 0xA000 0000. The ARM Cortex M0+ core revision is r0p0.
Content originally posted in LPCWare by Rorrik on Fri Jan 16 08:59:34 MST 2015 Okay, cool, so the value is not a boolean yes or no, it is a revision number of Cortex-M0+, good to know. Thanks!
Content originally posted in LPCWare by starblue on Fri Jan 16 02:44:03 MST 2015 There are two revisions of Cortex-M0+, r0p0 and r0p1. LPC81x uses r0p0, LPC82x r0p1. It's documented in the introductory chapters of the user manuals.
Content originally posted in LPCWare by Rorrik on Thu Jan 15 14:47:26 MST 2015 Does this mean that the LPC812 is not an ARM Cortex-M0+? Its data sheet implies that it is. If that is not what this #define means, then what does it mean?
Content originally posted in LPCWare by DF9DQ on Thu Jan 15 01:07:16 MST 2015 Let me add nn overly pedantic comment The core revisions of LPC81x and LPC82x are different:
Content originally posted in LPCWare by acv on Fri Jan 09 11:32:50 MST 2015 NXP just released a new version of the LPC812 that has the VTOR fix incorporated into the system.
Content originally posted in LPCWare by Rorrik on Fri Nov 14 08:55:23 MST 2014 Thanks! That's a much better answer. I think the other way was working fine, but now I understand better the problem. Thanks or the patch!
Content originally posted in LPCWare by acv on Thu Nov 13 11:46:46 MST 2014 Rorrik,
Here are the answers to your questions: 1) Can I change the VTOR on my device? Yes. 2) What would the syntax actually be for accessing this register? You have it right, the LPC open include files have a problem.
The issue is that the one include file is missing some information. Your original post doesn't give tool-chain details so I am going to make a few assumptions. If you post details, I can tailor the fix to your tool-chain. Here is the fix for the current version of LPC-open using Keil v5.12.
The LPC8xx specific cmsis.h file is broken. This can be found at ...\lpcopen\software\lpc_core\lpc_chip\chip_8xx\config.
At line 73 you fill find the following:
/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
#define __CM0_REV 0x0000/*!< Cortex-M0 Core Revision */
#define __MPU_PRESENT 0/*!< MPU present or not */
#define __NVIC_PRIO_BITS 2/*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0/*!< Set to 1 if different SysTick Config is used */
Here is the corrected section....
/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
#define __CM0PLUS_REV 0x0001/*!< Cortex-M0+ Core Revision */
#define __MPU_PRESENT 0/*!< MPU present or not */
#define __VTOR_PRESENT 1/*!< VTOR is present in this implementation */
#define __NVIC_PRIO_BITS 2/*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0/*!< Set to 1 if different SysTick Config is used */
Note there are two changes: [list=1] [*]__CM0_REV is changed to __CM0PLUS_REV, and the value is changed from 0 to 1. [*]The __VTOR_PRESENT define is added. [/list]
With these two changes, your original syntax will work. Note that the 82x has the same issue, so these changes are valid for that part as well.
These changes will be added to the next release of LPC open, which is due for the LPC8xx in the next week or so.
Content originally posted in LPCWare by MarcVonWindscooting on Wed Nov 12 14:53:25 MST 2014
*( (volatile uint32_t*) 0xE000ED08 ) = 0x1000;
I'm using VTOR in my LPC800 ramloader and it works. I think VTOR is optional in Cortex-M0 but it's implemented in LPC800. Another option is the hardware-remapping supported by many devices. However, distinguish between the two mechanisms, if your re-mapped code contains absolute addresses.
