SDRAM Init -- Fundamental Questions

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Tue Nov 06 12:07:19 MST 2012

  I have 3 very basic questions about SDRAM init on the 1778/1788.
 
  My board has two of Micron 256Mbit devices
  [16Mx16bits banks:4 rows:13 columns:9]
 
  Wired with Addr and control lines in common, one device providing
  the high 16 data bits, the other providing the low 16 data bits.
  I.e. the CPU data bus is 32bits (the devices are 16bits wide).
 
  Question 1:
  What Address Mapping should I be using?
 
  I would assume (for Row-Bank-Column):
  "1 0 011 01 = 256 Mbit (16Mx16), 4 banks, row length = 13, column length = 9"
  from table 132 in UM10470 rev 2
 
  and that the EMC controller will know I have two devices because
  the device width is half the cpu width.
 
  If this is not the case (and the cpu 'sees' a 16Mx32bit device,
  then there is no available mapping to get the correct bank/row/column
  setup! (What do I do then?)
 
  Question 2:
  What mode word shift factor should I be using?
 
  I would assume (9 columns + 2 bank bits + 2 for CPU data bus of 32bits)
  NOTE 2 = cpu data bus size which is NOT the same as the device data bus size!
  or should it be (cols+bank+1) due to the device width?
 
  Question 3:
 
  The EMC chapter in the user manual (UM10470 rev 2) defines all timings
  and delays in terms of "CCLK" I.e. the processor clock [120 MHz for me]
  and NOT in terms of "EMCCLK" [60 Mhz for me].
 
  Is this just incredibly slap-dash authoring, or do they REALLY mean the
  CPU clock -- even though this is (now) twice the speed of the EMCCLK?
 
  Anyone care to comment?
  Especially NXP Europe/USA (re the shockingly ambiguous manual!)

[lpcware]

Content originally posted in LPCWare by Dave on Wed Jun 05 09:46:25 MST 2013

LOL                            

Makes me happy somebody got something out of that post so long ago...  Thank you Mike :-)

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Sun May 26 10:40:26 MST 2013

Hi, I wrote my SDRAM init code in cortex M3 assembler; is that any good to you.

For various reasons, I am not able to post a complete canned compilable example,

but you might be able to get 'magic numbers' and the sequence of operations from it.

I also recommend you read this post by the awesome Dave http://www.lpcware.com/content/forum/dk-57vts-lpc1788-configuring-emc-sdram

I haven't been around this forum much the last month or so, but I will check for the next few days to see if you want anything from me.

Regards, Mike

[lpcware]

Content originally posted in LPCWare by alimicro on Tue May 14 05:46:26 MST 2013

Dear Mike

I have a problem with my SDRAM on LPC1788 controller board.

I've used <a style="font-family: Roboto, sans-serif; font-size: 13.63636302947998px; background-color: #ffffff;" href="http://www.embedinfo.com/en/list.asp?id=107">http://www.embedinfo.com/en/list.asp?id=107</a> as a reference design.

My circuit has 2xMT48LC16M16 in 32bit data structure and 64MByte memory space.

When I try to write a value, if I give much time to write (with gap time between each write) it is good but during a loop I will give wrong value on readback.

for example:

for(i=0;i&lt;1000;i++)

*wrptr=i;

has error

but 

for(i=0;i&lt;1000;i++){

*wrptr=i;

delayms(1);

}

has no error

would you please help me that what I sould do.

If you could send me your SDRAMinit function which is working properly I would appreciate it.

thanks in advance

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Fri Nov 09 12:49:16 MST 2012
Thanks Daniel, with your info and fixing a broken solder joint, I have a working SDRAM interface to my pair of Micron devices (MT48LC16M16-75) with an EMC clock of 60 MHz.

Cheers, Mike

[lpcware]

Content originally posted in LPCWare by Daniel Widyanto on Thu Nov 08 20:35:07 MST 2012
Hi,

Q1: Yes, it's correct. Use "256 Mbit (16Mx16), 4 banks, row length = 13, column length = 9" settings. The EMC IP will know that it's 32-bits wide memory, arranged in 16-bits upper and 16-bits lower byte, based on that setting.

Q2: It's (9 columns + 2 bit of banks + 2 for 32-bits).

The mode is based on "address" bus, not "data" bus. Hence, whether it's (16-bits x 2) or (32-bits x 1), it will have the same address shift for SDRAM MODE configuration. The app note in LPC32xx have clearer explanation on this (except that the burst rate for LPC177x must reach 128-bits..eg 16-bits x 8-burst). See http://www.nxp.com/documents/application_note/AN10935.pdf

Q3: I think the correct one should be based on EMCCLK, not CCLK. I will update people in documentation for this